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BEE3 Updates June 13 th , 2007

BEE3 Updates June 13 th , 2007. Chuck Thacker, John Davis Microsoft Research Chen Chang UC Berkeley. BEE3 Overview. 4 Xilinx FPGA: (FF1136) Virtex-5 LX110T or SX95T 16 DIMMs 2 DDR2-400/533/667 channels per FPGA Up to two 4GB DIMMs per channel 8 10GBase-CX4 interfaces

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BEE3 Updates June 13 th , 2007

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  1. BEE3 UpdatesJune 13th, 2007 Chuck Thacker, John Davis Microsoft Research Chen Chang UC Berkeley

  2. BEE3 Overview • 4 Xilinx FPGA: (FF1136) • Virtex-5 LX110T or SX95T • 16 DIMMs • 2 DDR2-400/533/667 channels per FPGA • Up to two 4GB DIMMs per channel • 8 10GBase-CX4 interfaces • 4 PCI-E x8 slots (endpoints) • 4 QSH-DP (40 LVDS pairs) daughter card & cable connectors • 4 GE RJ45 interfaces • 2U chassis • ATX12V/EPS2U 500W power supply

  3. BEE3 Package ATX PWR FPGA I/O modules PCIe Cards June 2007 RAMP Tutorial

  4. BEE3 Package Front View • Data I/Os: • 4 PCIe slots • 8 CX4 connectors • 4 RJ45 • 4 FPGA done LEDs • 4 FPGA user LEDs • Control I/O Panel: • 4 RS232(RJ45) • 4 SD card slots • 1 CF card (SystemACE) • 1 Xilinx USB-JTAG • 2 SMA clock input • 1 Power reset • 1 FPGA soft reset June 2007 RAMP Tutorial

  5. FPGA I/O Interfaces

  6. COTS PCI-Express over Cable Solution from One Stop Systems HIB2 x8 Host PCIe x8 cable Up to 7 meters HIB2 x8 Target

  7. Peak I/O Bandwidths (per-FPGA)(estimates for XC5VLX110T-1 part) • DDR2 Memory • 400 MT/s * 8B/T * 2 channels: 6.4 GB/s • Ring • 400 MT/s * 8 B/T * 2 channels: 6.4 GB/s • QSH • 400 MT/s * 4 B/T: 1.6 GB/s • Ethernet • 125 MB/s • CX4 • 1.25 GB/s * full duplex * 2 channels: 5GB/s • PCI Express x8 • 2GB/s * full duplex: 4GB/s June 2007 RAMP Tutorial

  8. Schedule • Generate Specification – Done • Schematic Entry – Done • Board Layout – Started • Thermal modeling, heat sink design – Started • Chassis design -- Started • Signal Integrity – Imminent • Prototypes: Late Summer – Bring-up starts • Production: Start early 2008 June 2007 RAMP Tutorial

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