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# ECE 4110–5110 Digital System Design - PowerPoint PPT Presentation

ECE 4110–5110 Digital System Design. Lecture #19 Agenda MSI: Ripple Carry Adders Announcements Test1 Statistics: Count 13, Average 84, Maximum possible 102, Grades 4 A, 7 B, 1 C, 1 D Maximum MedianMinimum CmpE978680 EE908169 Next HW#9. Ripple Carry Adder.

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ECE 4110–5110 Digital System Design

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### ECE 4110–5110 Digital System Design

Lecture #19

• Agenda

• Announcements

• Test1 Statistics:

Count 13, Average 84, Maximum possible 102, Grades 4 A, 7 B, 1 C, 1 D

Maximum MedianMinimum

• CmpE978680

• EE908169

• Next HW#9

• Addition – Half Adder- one bit addition can be accomplished with an XOR gate (modulo sum 2) 0 1 0 1 +0+0+1+1 0 1 1 10- notice that we need to also generate a “Carry Out” bit- the “Carry Out” bit can be generated using an AND gate- this type of circuit is called a “Half Adder”- it is only “Half” because it doesn’t consider a “Carry In” bit

• Addition – Full Adder- to create a full adder, we need to include the “Carry In” in the SumCin A BCoutSum 0 0 0 0 0 0 0 1 0 1 Sum = A  B  Cin 0 1 0 0 1 Cout = Cin∙A + A∙B + Cin∙B 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1- you could also use two "Half Adders" to accomplish the same thing

• Addition – Ripple Carry Adder- cascading Full Adders together will allow the Cout’s to propagate (or Ripple) through the circuit- this configuration is called a Ripple Carry Adder