- 102 Views
- Uploaded on
- Presentation posted in: General

ECE 4110–5110 Digital System Design

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Lecture #19

- Agenda
- MSI: Ripple Carry Adders

- Test1 Statistics:
Count 13, Average 84, Maximum possible 102, Grades 4 A, 7 B, 1 C, 1 D

Maximum MedianMinimum

- CmpE978680
- EE908169

- Next HW#9

- Addition – Half Adder- one bit addition can be accomplished with an XOR gate (modulo sum 2) 0 1 0 1 +0+0+1+1 0 1 1 10- notice that we need to also generate a “Carry Out” bit- the “Carry Out” bit can be generated using an AND gate- this type of circuit is called a “Half Adder”- it is only “Half” because it doesn’t consider a “Carry In” bit

- Addition – Full Adder- to create a full adder, we need to include the “Carry In” in the SumCin A BCoutSum 0 0 0 0 0 0 0 1 0 1 Sum = A B Cin 0 1 0 0 1 Cout = Cin∙A + A∙B + Cin∙B 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1- you could also use two "Half Adders" to accomplish the same thing

- Addition – Ripple Carry Adder- cascading Full Adders together will allow the Cout’s to propagate (or Ripple) through the circuit- this configuration is called a Ripple Carry Adder

- Addition – Ripple Carry Adder- What is the delay through the Full Adder? - Each Full Adder has the following logic: Sum = A B Cin Cout = Cin∙A + A∙B + Cin∙B - tFull-Adder will be the longest combinational logic delay path in the adder

- Addition – Ripple Carry Adder- What is the delay through the entire iterative circuit? - the delay increases linearly with the number of bits , so: tRCA = n·tFull-Adder
- Faster technologies (e.g. AHCT vs HCT) can be used to reduce tFull-Adder, but they still suffer linear delay effect
- Different topologies exist to reduce total delay.