PowerPC 601. Stephen Tam. To be tackled today. Architecture Execution Units Fixed-Point (Integer) Unit Floating-Point Unit Branch Processing Unit Cache Unit Memory Management Unit (MMU) Pipeline Structure Instruction buffer Multiply-Add Benchmark. PowerPC Processors.
Byte/halfword load and store
# of Integer registers
Integer register size
# of Floating point registers
Floating point register size
Floating point format
IEEE 32 bit, 64 bit
32/64 bit mode bit
Instruction/data cache size
Fetch Up to eight instructions are fetched into an instruction buffer
Dispatch Instructions are dispatched to either the FXU or FPU
Decode Instructions are decoded, with the source registers being read
Instructions to the FXU are decoded together in the dispatch stage.
Execute This stage exists in the BPU as well as the FXU, where integer instructions execute and cache lookup and address processing also occur
Execute1 FPU multiplication
Execute2 FPU addition
Cache Floating-point operands are sent to the FPU and the integer operands are sent to the FXU.
Write Register file write.
IEEE- Computer, June 1994, Vol. 27, No. 6, Page 46-58
Microprocessor Report, May 8, 1995