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EE115C – Spring 2010 Digital Electronic Circuits

EE115C – Spring 2010 Digital Electronic Circuits. Final Project Presentation. Area-Delay Optimization for a 10-bit Carry-Select Adder. Design Summary. A) Adder block topology, B) Circuit Style A) Used mirror adder, B) Static

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EE115C – Spring 2010 Digital Electronic Circuits

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  1. EE115C – Spring 2010Digital Electronic Circuits Final Project Presentation

  2. Area-Delay Optimization for a 10-bit Carry-Select Adder

  3. Design Summary • A) Adder block topology, B) Circuit StyleA) Used mirror adder, B) Static • C) WHY: about Area, about Delay, otherC) Static is easier to size, can optimize for delay easier, low power consumption because it’s static Note: tp = max {tp_ci→co, tp_ci→s9} Area = max {X2, Y2} EE115C – Spring 2010

  4. Critical Path Analysis • Highlight critical path • block diagram of design / crit-path delay equation Image source: http://en.wikipedia.org/wiki/Carry_select_adder EE115C – Spring 2010

  5. Design Optimization w=1.26u • Swept inverter based on width • Found that 3.5:1 ratio better for circuit, based on load given w=1.26u w=840n w=840n w=1.26u w=420n w=360n w=120n w=240n w=240n w=360n w=360n w=120n w=420n EE115C – Spring 2010

  6. Functionality Check • Screenshot of relevant waveforms EE115C – Spring 2010

  7. Adder Layout X=66.5µm, Y=35.1µm, Area = 4422µm2 EE115C – Spring 2010

  8. Discussion • Three most important features of your design • Used static for low-power consumption • Used symmetry with mirror adder grouping to reproduce wiring easily • Used mirror adder to reduce area • Given another chance, 3 things you would do different • Could have made layout more compact by using more metals 4 and 5 • If delay is more important than power consumption, would have used transmission gate rather static • Put in some buffers to optimize design EE115C – Spring 2010

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