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2006 ITRS Public Conference Emerging Research Devices Hsinchu, Taiwan Ambassador Hotel December 5, 2006. Jim Hutchby – SRC. ITRS Emerging Research Devices Working Group. Mike GarnerIntel Makoto Yoshimi SOITEC Kristin De MeyerIMEC Tak Ning IBM Philip WongStanford U.

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2006 ITRS Public Conference Emerging Research Devices Hsinchu, Taiwan Ambassador Hotel

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2006 itrs public conference emerging research devices hsinchu taiwan ambassador hotel

2006 ITRS Public Conference

Emerging Research Devices

Hsinchu, Taiwan

Ambassador Hotel

December 5, 2006

Jim Hutchby – SRC


Itrs emerging research devices working group

ITRS Emerging Research Devices Working Group

  • Mike GarnerIntel

  • Makoto Yoshimi SOITEC

  • Kristin De MeyerIMEC

  • Tak Ning IBM

  • Philip WongStanford U.

  • Luan TranMicron

  • Victor ZhirnovSRC

  • Simon Deleonibus LETI

  • Thomas Skotnicki ST Me

  • Yuegang ZhangIntel

  • Kentaro Shibahara Hiroshima U.

  • Philippe CoronelST Me

  • Phil KuekesHP

  • Christian GamratCEA

  • Dan HerrSRC

  • Dave RobertsAir Products

  • Ken UchidaToshiba

  • Shin-ichi TakagiU. Tokyo

  • Yasuo WadaWaseda U.

  • Hiroyugi AkinagaAIST

  • Matsuo HidakaISTEK

  • Satoshi SugaharaTokyo Tech

  • Tetsuya AsaiHokkaido U.

  • Wei-Xin NiNDL

  • George BourianoffIntel/SRC

  • Joe BrewerU. Florida

  • Toshiro HiramotoU. Tokyo

  • Jim HutchbySRC

  • Mike Forshaw UC London

  • Rainer WaserRWTH A

  • In YooSamsung

  • Lothar RischInfineon

  • Peter ZeitzoffFreescale

  • Murali Ramachandran Freescale

  • Erik DeBenedictisSNL

  • Lou LomeIDA

  • U-In ChungSamsung

  • In-Seok YeoSamsung

  • Ralph CavinSRC

  • Zoran KrivokapicAMD

  • Hiroshi MizutaTokyo Tech

  • Seiichiro KawamuraSelete

  • Hiroshi KotakiSharp

  • Yuji AwanoFujitsu

  • Kojiro YagamiSony

  • Shigenori HayashiMatsushita

  • Yasuo InoueRenesas Tech

  • Fumiyuki NiheiNEC


2006 itrs public conference emerging research devices hsinchu taiwan ambassador hotel

New Materials

Model Knowledge

0

1

Scope of Emerging Research Devices2006/7

New Memory

and Logic

Technologies

New

Architecture

Technologies

Nanotubes

Molecular devices

Spin states

Emerging Information Processing Concepts


Emerging research devices organization component tasks 2007

Create a New Chapter in 2007

Emerging Research DevicesOrganization & Component Tasks (2007)

Emerging Research Devices

Emerging

Materials

Emerging

Logic and Memory

Devices

Emerging

Architectures


2006 erd erm workshops co sponsored by nsf

2006 ERD/ERM WorkshopsCo-sponsored by NSF


What are we looking for

Required characteristics:

Scalability

Performance

Energy efficiency

Gain

Operational reliability

Room temp. operation

Preferred approach:

CMOS process compatibility

CMOS architectural compatibility

What are we looking for?

Alternative state variables (Beyond Charge State)

  • Spin state

  • Molecular state

  • Strongly correlated electron state

  • Atomic quantum state

  • Electric dipole orientation

  • Magnetic flux quanta

  • Mechanical deformation

  • Photon (intensity, phase, ..)

Alternative state variables

  • Spin–electron, nuclear, photon

  • Phase

  • Quantum state

  • Magnetic flux quanta

  • Mechanical deformation

  • Dipole orientation

  • Molecular state


2005 itrs erd table 57 emerging research memory devices demonstrated and projected parameters

Transfer to PIDS

2005 ITRS ERD: Table 57 Emerging Research Memory Devices Demonstrated and Projected Parameters


Critical evaluation memory

> 20

>16 - 18

>18 - 20

< 16

For each Technology Entry (e.g. 1D Structures, sum horizontally over the 8 Criteria

Max Sum = 24

Min Sum = 8

Critical EvaluationMemory


Table 57a capacitance based memory technologies

Table 57a: Capacitance-based memory technologies


Table 57b resistance based memory technologies

Table 57b: Resistance-based memory technologies


Example cnt cross bar memory

Example – CNT cross-bar memory

Rueckes T. et al., SCIENCE 289 (5476): 94-97 JUL 7 2000

Moving Atoms

Concept

  • Each memory element is based on suspended crossed carbon nanotubes.

  • Cross-bar array of CNT forms mechanically bi-stable, electrostatically-switchable device elements at each cross point.

  • The memory state is read out as the junction resistance.

Expectations: n=1012 bits/cm2, f=100 GHz


Memory technologies for 2007 new erd chapter

Numerical data will be updated

We will have two tables for Emerging Research Memory Technology Entries:

Capacitance-based memory technologies

Resistance-based technologies.

Put nanomechanical memory into the new tables

Transfer Nanofloating Gate Entry to PIDS/Transition Table.

Memory Technologies for 2007 new ERD Chapter


2005 itrs erd table 59 emerging research logic devices demonstrated and projected parameters

Sub-

Categorize

Molecular

and Spin

2005 ITRS ERD: Table 59 Emerging Research Logic Devices Demonstrated and Projected Parameters


Sub categories for spin and molecular devices

Spin

Domain wall manipulation

Ferromagnetic phase change (nano-domains)

Spin transport modulation

Spin torque transfer

Individual and or collective spin manipulation

Molecular devices

Crossbar coupling elements

Molecular logic elements and interconnects

Intra molecular logic elements

Sub-categories for Spin and molecular devices


Critical evaluation logic

> 20

>16 - 18

>18 - 20

< 16

For each Technology Entry (e.g. 1D Structures, sum horizontally over the 8 Criteria

Max Sum = 24

Min Sum = 8

Critical EvaluationLogic


Logic device conclusions

Conclusions from ERD Logic Devices Workshop(September 21, 2006)

Logic device conclusions

  • Continued analysis of alternative technology entries likely will continue to yield the same result:

    • Nothing beats MOSFETs overall for performing Boolean logic operations at comparable risk levels

  • Certain functions, e.g. image recognition (associative processing), may be more efficiently done in networks of non-linear devices rather than Boolean logic gates

    • “Plasticity” of nonlinearity may be potentially useful


Supplementing cmos

Basis of Existing Assessments of Logic Devices

A possible ultimate evolution of on-chip architectures is Asynchronous Heterogeneous Multi-Core with Hierarchical Processors Organization

MF(n) – application-specific processor implementing a specific macro-function (may need specialized devices)

General Purpose Processor

MF1

MF2

MF3

MF4

General

Purpose

Processor

MF12

MF5

MF11

MF6

MF10

MF9

MF8

MF7

Supplementing CMOS


Proposed new focus of logic section

Consider new logic technologies that supplement CMOS to provide enhanced hardware capability and can be optimally executed with alternative devices

Determine appropriate metric and compare to Si on the specialized application

Determine if proposed application contains a standard set of “macro-functions”

Understand the performance of the device in terms of its non-linear characteristics

Think in terms of heterogeneous co-processors integrated with traditional CPU

Proposed new focus of Logic Section


Potential supplemental applications

Image recognition

Speech recognition

DSP (cross correlation)

Data Mining

Optimization

Physical simulation

Sensory data processing (biological, physical)

Image creation

Cryptographic analysis

Potential supplemental applications


Messages

Preparing for the 2007 re-write of the ERD Chapter.

Conducted four workshops in 2006 on Emerging Research Memory, Logic, Architectures and Materials (co-sponsored by ITRS and NSF)

Considering new Technology Entries and transfers to PIDS & FEP in 2007

Materials Section: Spin out a new cross-cut chapter on Emerging Research Materials.

Memory Section: Will add NEMS mechanical memory to section.

Divide Emerging Memory Tables into Resistive and Capacitive subcategories

Update section in 2007

Logic Section: Considering reformulation of Logic Device Section to encourage high potential, but high risk approaches while maintaining Technology Entry evaluation function.

Create subcategories for key Technology Entries (e.g. Spin & Molecular logic)

Re-considering status of candidate Technology Entries (e.g. RSFQ Logic)

Re-structuring Logic Section via Emerging Logic Workshop in September.

Messages


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