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2006 ITRS Public Conference Emerging Research Devices Hsinchu, Taiwan Ambassador Hotel December 5, 2006. Jim Hutchby – SRC. ITRS Emerging Research Devices Working Group. Mike Garner Intel Makoto Yoshimi SOITEC Kristin De Meyer IMEC Tak Ning IBM Philip Wong Stanford U.
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Scope of Emerging Research Devices2006/7
Emerging Information Processing Concepts
Emerging Research Devices
Logic and Memory
Room temp. operation
CMOS process compatibility
CMOS architectural compatibilityWhat are we looking for?
Alternative state variables (Beyond Charge State)
Alternative state variables
Rueckes T. et al., SCIENCE 289 (5476): 94-97 JUL 7 2000
Expectations: n=1012 bits/cm2, f=100 GHz
We will have two tables for Emerging Research Memory Technology Entries:
Capacitance-based memory technologies
Put nanomechanical memory into the new tables
Transfer Nanofloating Gate Entry to PIDS/Transition Table.Memory Technologies for 2007 new ERD Chapter
and Spin2005 ITRS ERD: Table 59 Emerging Research Logic Devices Demonstrated and Projected Parameters
Domain wall manipulation
Ferromagnetic phase change (nano-domains)
Spin transport modulation
Spin torque transfer
Individual and or collective spin manipulation
Crossbar coupling elements
Molecular logic elements and interconnects
Intra molecular logic elementsSub-categories for Spin and molecular devices
A possible ultimate evolution of on-chip architectures is Asynchronous Heterogeneous Multi-Core with Hierarchical Processors Organization
MF(n) – application-specific processor implementing a specific macro-function (may need specialized devices)
General Purpose Processor
Determine appropriate metric and compare to Si on the specialized application
Determine if proposed application contains a standard set of “macro-functions”
Understand the performance of the device in terms of its non-linear characteristics
Think in terms of heterogeneous co-processors integrated with traditional CPUProposed new focus of Logic Section
Conducted four workshops in 2006 on Emerging Research Memory, Logic, Architectures and Materials (co-sponsored by ITRS and NSF)
Considering new Technology Entries and transfers to PIDS & FEP in 2007
Materials Section: Spin out a new cross-cut chapter on Emerging Research Materials.
Memory Section: Will add NEMS mechanical memory to section.
Divide Emerging Memory Tables into Resistive and Capacitive subcategories
Update section in 2007
Logic Section: Considering reformulation of Logic Device Section to encourage high potential, but high risk approaches while maintaining Technology Entry evaluation function.
Create subcategories for key Technology Entries (e.g. Spin & Molecular logic)
Re-considering status of candidate Technology Entries (e.g. RSFQ Logic)
Re-structuring Logic Section via Emerging Logic Workshop in September.Messages