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Joseph Schneider February 23, 2010

Joseph Schneider February 23, 2010. Bridge Floating-Point Fused Multiply-Add Design By Eric Quinnell , Earl E Swartzlander Jr., and Carl Lemonds. Fused M ultiply-Add (FMA) is a unit designed to perform (A x B) + C as a single instruction

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Joseph Schneider February 23, 2010

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  1. Joseph Schneider February 23, 2010 Bridge Floating-Point Fused Multiply-Add DesignBy Eric Quinnell, Earl E Swartzlander Jr., and Carl Lemonds

  2. Fused Multiply-Add (FMA) is a unit designed to perform (A x B) + C as a single instruction Faster, more precise than using two consecutive instructions with standard multiplier and adder Can perform standard addition and multiplication with appropriate constants Fused Multiply-Add

  3. Performing standard addition and multiplication suffers greater latencies than when using a standard adder or multiplier When using an FMA instead, can’t perform addition and multiplication in parallel Fused Multiply-add

  4. Goal: To design architecture between FADD and FMUL units. Reuse components to minimize area and power consumption Allow both standard operations and the FMA functionality fused multiply-add

  5. Floating-point units all assume double-precision (64-bit) IEEE-754 standard format format

  6. Compare adder standalone, multiplier standalone, FMA standalone, and the FMA bridge Compared on basis of latency, area, and power Basis of comparison

  7. (A x B) + C A and B multiplied while C is aligned based on exponent difference Carry-save adder implemented Result is rounded- only once as opposed to two roundings necessary for performing the equation in two operations FMA architecture

  8. Follows same architecture of FMA, only reusing parts from FADD and FMUL as appropriate From FMUL, uses multiplier array. From FADD, uses rounding unit. In this method, FADD and FMUL can be used individually or in parallel, while the FMA is used only when needed. Clock-gating used to ensure bridge is only powered when needed Bridge FMA

  9. Same as a standard unit, only with additional outputs from multiplier array leading to FMA Round element shut down via clock-gating when performing an FMA operation FMUL

  10. Uses Farmwald dual-path FADD design; Two paths available based on exponent difference of inputs Multiplexer used to select between paths for rounding unit now include option for FMA input In this manner, FMA uses FADD’s rounding unit FADD

  11. End result, Bridge FMA hardware is essentially the original FMA hardware, only without the multiplier array and rounding unit. Bridge FMA

  12. FMUL, FADD, FMA, and Bridge FMA all implemented in Verilog Uses AMD 65-nm silicon-on-insulator design set results

  13. Bridge architecture 30%-70% faster than FMA architecture when performing FADD or FMUL instructions with significant savings in power consumption Also allows for an FADD and FMUL instruction in parallel, further improving speed 12% performance gain when executing FMA instruction over consecutive operations on individual FADD and FMUL. results

  14. Takes 40% more area to include Bridge FMA with FADD and FMUL Unit 60% increase in power for FMA instruction over consecutive FADD and FMUL instructions in worst case conditions Increased latency and power over standalone FMA unit Results

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