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Chapter One Introduction to Pipelined Processors

Chapter One Introduction to Pipelined Processors. Principle of Designing Pipeline Processors. (Design Problems of Pipeline Processors). State Diagram. Shortcut Method of finding Latency. Forbidden Latency Set,F = {5} U {2} U {2} = { 2,5}. State Diagram.

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Chapter One Introduction to Pipelined Processors

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  1. Chapter One Introduction to Pipelined Processors

  2. Principle of Designing Pipeline Processors (Design Problems of Pipeline Processors)

  3. State Diagram

  4. Shortcut Method of finding Latency • Forbidden Latency Set,F = {5} U {2} U {2} = { 2,5}

  5. State Diagram • The initial collision vector (ICV) is a binary vector formed from F such that C = (Cn…. C2 C1) where Ci = 1 if i  F and Ci = 0 if otherwise • Thus in our example F = { 2,5 } C = (1 0 0 1 0)

  6. State Diagram • The procedure is as follows: • Start with the ICV • For each unprocessed state, For each bit i in the CVi which is 0, do the following: • Shift CVi right by i bits • Drop i rightmost bits

  7. State Diagram • Append zeros to left • Logically OR with ICV • If step(d) results in a new state then form a new node for this state and join it with node of CVi by an arc with a marking i. • This shifting process needs to continue until no more new states can be generated.

  8. State Diagram 1 0 0 1 0

  9. State Diagram 1 0 0 1 0 i = 1 ICV – 10010 OR CVi – 01001 CV* 11011 1 1 0 1 1 1

  10. State Diagram 1 0 0 1 0 3 i = 3 1 ICV – 10010 OR CVi – 00010 CV* 10010 1 1 0 1 1

  11. State Diagram 1 0 0 1 0 3 i = 4 1 4 1 0 0 1 1 1 1 0 1 1 ICV – 10010 OR CVi – 00001 CV* 10011

  12. State Diagram 5 1 0 0 1 0 3 i = 5 1 4 1 0 0 1 1 1 1 0 1 1 ICV – 10010 OR CVi – 00000 CV* 10010

  13. State Diagram 5 1 0 0 1 0 3 4 3 1 1 0 0 1 1 1 1 0 1 1 i =3 ICV – 10010 OR CVi – 00010 CV* 10010

  14. State Diagram 5 1 0 0 1 0 3 4 3 1 4 1 0 0 1 1 1 1 0 1 1 i =4 ICV – 10010 OR CVi – 00001 CV* 10011

  15. State Diagram 5 1 0 0 1 0 3 4 3 1 4 1 0 0 1 1 1 1 0 1 1 3 i =3 ICV – 10010 OR CVi – 00011 CV* 10011

  16. State Diagram 5+ 1 0 0 1 0 3 5+ 4 3 1 4 1 0 0 1 1 1 1 0 1 1 3 i = 5 ICV – 10010 OR CVi – 00000 CV* 10010

  17. State Diagram 5+ 1 0 0 1 0 3 5+ 4 5+ 3 1 4 1 0 0 1 1 1 1 0 1 1 3 i = 5 ICV – 10010 OR CVi – 00000 CV* 10010

  18. State Diagram • The state with all zeros has a self-loop which corresponds to empty pipeline and it is possible to wait for indefinite number of latency cycles of the form (7),(8), (9),(10) etc. • Simple Cycle: latency cycle in which each state is encountered only once. • Complex Cycle: consists of more than one simple cycle in it. • It is enough to look for simple cycles

  19. State Diagram • Greedy Cycle: A simple cycle is a greedy cycle if each latency contained in a cycle is the minimal latency(outgoing arc) from a state in the cycle. • A good task initiation sequence should include the greedy cycle.

  20. Simple cycles & Greedy cycles • The Simple cycles are? • The Greedy cycles are ?

  21. Simple cycles & Greedy cycles • The simple cycles are (3),(5) ,(1,3,3),(4,3) and (4) • The Greedy cycle is (1,3,3)

  22. State Diagram • In the above example, the cycle that offers MAL is (1, 3, 3) (MAL = (1+3+3)/3 =2.333)

  23. UQ: Problem • Consider the reservation table given below

  24. Problem • Find the forbidden set of latencies • State the collision vector • Draw the state transition diagram • List simple cycles and greedy cycles • Calculate MAL (minimum average latency)

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