Elastic circuits blending synchronous and asynchronous technologies
Sponsored Links
This presentation is the property of its rightful owner.
1 / 128

Elastic Circuits blending synchronous and asynchronous technologies PowerPoint PPT Presentation


  • 90 Views
  • Uploaded on
  • Presentation posted in: General

Elastic Circuits blending synchronous and asynchronous technologies. Jordi Cortadella Universitat Politècnica de Catalunya, Barcelona (joint work with M. Kishinevsky and M. Galceran-Oms ) Collège de France May 21 st , 2013. … t ime is elastic …. S ynchronous circuit. Flip Flops.

Download Presentation

Elastic Circuits blending synchronous and asynchronous technologies

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Elastic Circuitsblending synchronous and asynchronous technologies

Jordi Cortadella

Universitat Politècnica de Catalunya, Barcelona

(joint work with M. Kishinevsky and M. Galceran-Oms)

Collège de FranceMay 21st, 2013


… time is elastic …

Elastic circuits


Synchronous circuit

Flip Flops

CombinationalLogic

Flip Flops

PLL

Elastic circuits


Asynchronous circuit

L

CombinationalLogic

L

C

C

delay

4-phase

Elastic circuits


Asynchronous circuit

ReqIn

ReqOut

C

C

C

C

AckOut

AckIn

  • David Muller’s pipeline (late 50’s)

  • Sutherland’s Micropipelines (Turing award, 1989)

Elastic circuits


Globally-asynchronousLocally-synchronous

GALS


SoC design with GALS

  • Most IPs are synchronous

  • Different components may have different operating frequencies

  • Some components have variable latencies (e.g., cache hit/miss latency)

  • Multiple clock domains are essential

DSP

P

CLK3

Bridge

Bridge

CDC

CDC

Fast Bus

CLK1

Mem

CLK2

Slow Bus

Elastic circuits


Multiple clock domains

Independent clocks

Rational clockfrequencies

Single clock(mesochronous)

CLK1

f1/f0

CLK

(f0)

f2/f0

CLK2

CLK0

CLK

f3/f0

CLK3

(controllable skew)

Elastic circuits


Synchronous handshakes

Sender

Receiver

Data

Valid

Ack

CLK1

CLK2

  • The arrival of data is unpredictable

  • Handshakes solve the problem

Elastic circuits


The problem: metastability

D

Q

D

Q

CLKS

CLKR

setup

hold

CLKR

D

Q

?

Elastic circuits


Metastability

Source: W. J. Dally, Lecture notes for EE108A, Lecture 13.Metastability and Synchronization Failure (or When Good Flip-Flops go Bad) 11/9/2005.

Elastic circuits


Metastability

logic 0

logic 1

metastable

Elastic circuits


Classical synchronous solution

D

Q

D

Q

D

Q

D

Q

CLKT

CLKR

Mean Time Between Failures

fФ:frequency of the clock

fD:frequency of the data

tr:resolve time available

W:metastability window

:resolve time constant

Example

Elastic circuits


Handshake with synchronizers

Sender

Receiver

Data

Valid

Ack

CLK1

CLK2

  • Simple solution

  • Throughput can be highly degraded:a long round trip for every transaction

Elastic circuits


Asynchronous FIFOs

Circular buffer

Data

Data

3-4 cycles

1 cycle

1 cycle

Valid

Valid

FIFO control

Ack

Ack

Clk Out

Clk In

  • Ack is issued as soon as data has been delivered

  • No impact on throughput (1 token/cycle)

  • Min latency determined by the internal synchronizers

  • Some tricky structures for the FIFO pointers (e.g. Grey encoding)

Elastic circuits


SoC design with GALS

  • Bridges for Clock Domain Crossing usually contain asynchronous FIFOs

  • Latency cost only when interfacing with synchronous domains

  • No latency penalty between asynchronous domains

DSP

P

CLK3

Bridge

Bridge

CDC

CDC

Fast Bus

CLK1

Mem

CLK2

Slow Bus

Elastic circuits


Synchronous and Asynchronousmeeting each other


Meanwhile, a small village ofindomitable engineers was resisting the synchronous occupation …

Asynchronia

Elastic circuits


Bill Grundmann(Intel’s director of CAD research,

Technical director for CAD technology for the Alpha Microprocessor):

“The specification of a complex system is usuallyasynchronous (functional units, messages, queues, …),

… however the clock appears when we move downto the implementation levels”

(in a technical discussion about system designwithM. Kishinevskyand J. Cortadella, 2004)

Elastic circuits


Async and Sync meeting each other

Async

  • Modular (time elasticity)

  • But hard to analyze and synthesize

J. O’Leary and G. Brown, 1997Synchronous emulation of asynchronous circuits

A. Peetersand K. Van Berkel, 2001

Synchronous handshake circuits

Elastic Circuits(Sync / Async)

Cortadella et al., Desynchronization, 2003

L. Carloni et al., 1999A methodology for correct-by-construction latency-insensitive design

  • Easy to analyze and synthesize

  • Not modular (time rigid)

Sync

Elastic circuits


Different flavors of elasticity

+

Rigid

4

7

1

4

8

3

time

0

1

2

4

+

7

1

a

3

4

8

0

1

2

Asynchronous

7

1

4

1

2

0

+

e

8

4

3

Synchronous Elastic

Elastic circuits


Why synchronous elasticity?

  • Time is discrete (cycle based), but unpredictable (unknown number of cycles)

  • Examples

    • Short/long integer addition (8 bits, 64 bits)

    • Floating-point units

    • Cache latency: fast hit(2), slow hit(3), miss(>20)

    • Bus arbitration

    • Latencies in Network-on-Chip

    • … and many others

Elastic circuits


… even at design time

Sender

Receiver

CLK

Can we add a register without modifying the functionality of the system?

Elastic circuits


Many systems are already elastic

AMBA AXI bus protocol

Handshake signals

Elastic circuits


Designing withsynchronous elasticity


Communication channel

sender

receiver

Data

Data

Long wires: slow transmission

Elastic circuits


Pipelined communication

Data

sender

receiver

Data

How about if the sender does not always send valid data?

Elastic circuits


Pipelined communication

Data

sender

receiver

Data

Elastic circuits


Pipelined communication

Data

sender

receiver

Data

Elastic circuits


Pipelined communication

Data

sender

receiver

Data

Elastic circuits


Pipelined communication

Data

sender

receiver

Data

???

Elastic circuits


The Valid bit

sender

receiver

Data

Data

Valid

Valid

Elastic circuits


The Valid bit

Data

Valid

sender

receiver

Data

Valid

Elastic circuits


The Valid bit

Data

Valid

sender

receiver

Data

Valid

Elastic circuits


The Valid bit

Data

Valid

sender

receiver

Data

Valid

Elastic circuits


The Valid bit

Data

Valid

sender

receiver

Data

Valid

How about if the receiver is not always ready ?

Elastic circuits


The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

0

0

Elastic circuits


The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

1

1

Elastic circuits


The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

1

1

1

Elastic circuits


The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

1

1

1

1

1

Back-pressure

Elastic circuits


The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

1

1

1

1

0

Elastic circuits


The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

0

0

Elastic circuits


The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

0

0

Elastic circuits


The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

0

0

Elastic circuits


The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

0

0

Elastic circuits


The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

0

1

Long combinational path

Elastic circuits


Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

  • Handshakes with short wires

  • Double storage required

Elastic circuits


Flip-flops vs. latches

sender

receiver

FF

FF

1 cycle

Elastic circuits


Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Elastic circuits


Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Elastic circuits


Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Elastic circuits


Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Elastic circuits


Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Elastic circuits


Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Elastic circuits


Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Flip-flops already have a

double storage capability, but …

Elastic circuits


Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Not allowed in conventional

FF-based design !

Elastic circuits


Flip-flops vs. latches

H

L

H

L

sender

receiver

1 cycle

Let’s make the master/slave latches independent

Elastic circuits


Flip-flops vs. latches

H

L

H

L

sender

receiver

½ cycle

½ cycle

Let’s make the master/slave latches independent

Only half of the latches (H or L) can move tokens

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

Valid

Valid

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

0

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

0

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

0

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

0

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

0

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Basic VS block

Eni

Eni

Vi-1

Vi

Vi-1

Vi

VS

Si-1

Si

Si-1

Si

Elastic circuits


Elastic netlists

Enable signal

to data latches

V

S

VS

Fork

V

S

Join

VS

Join / Fork

VS

V

S

V

S

VS

Elastic circuits


Join

+

V1

VS

V

VS

S1

VS

S

V2

VS

VS

S2

Elastic circuits


Lazy Fork

V

V1

S1

V2

S

S2

Elastic circuits


Eager Fork

S1

^

V1

V

V2

^

S

S2

Elastic circuits


Variable Latency Units

V/S

V/S

[0 - k] cycles

done

clear

go

Elastic circuits


Design automation


Transforming sync into elastic

Elastic circuits


Transforming sync into elastic

Elastic circuits


Transforming sync into elastic

Behavioralequivalenceis preserved

Elastic circuits


Elastic Esterel

module ABRO:

input A,B,R;

output O;

loop

[ await A || await B ];

emit O

each R

end module

Marc GalceranOms, Master thesis, 2007

Elastic circuits


Elastic Esterel

A

PauseReg7

R

O

Boot

B

PauseReg11

Elastic circuits


Elastic Esterel

A

PauseReg7

R

O

Boot

B

PauseReg11

Elastic Control Layer

Valid_A

Stop_A

Valid_B

Valid_O

Stop_B

Stop_O

Valid_R

Stop_R

Elastic circuits


Circuit vs. μarchitectural cycles

Elastic circuits


Synchronous handshake circuits (Peeters, 2001)

int = type [0..255]& gcd: main proc(in? chan <<int,int>> & out! chanint)begin x, y: varint| forever do in?<<x,y>> ; do x <> y thenif x < y then y:=y-xelse x:=x-yfiod ; out!xodend

Sources:

J. Kessels and A. Peeters.DESCALE: A Design Experiment for a SmartCard Application Consuming Low Energy,in Principles of Asynchronous Circuit Design, A Systems Perspective,Eds., J. Sparso and S. Furber, Kluwer Academic Publishers, 2001.

P.A.Beerel, R.O. Ozdag and M. Ferretti.A Designer’s Guide to Asynchronous VLSI,Cambridge University Press, 2010.

Elastic circuits


Generalization: bounded FIFOs

Out

In

B3

B1

B2

Bounded Dataflow Networks

Elastic circuits


Behavioral equivalence

Synchronous:

D: a b c d e f g h i j k …

Elastic:

D: a a b bb c d e e f g g h iii j k …

V: 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 …

Elastic circuits


Early evaluation


Early evaluation

3

x

15

2

5

Elastic circuits


Early evaluation

3

x

6

2

Elastic circuits


Early evaluation

0

x

0

8

Elastic circuits


Early evaluation

  • Only wait for required inputs

  • Late arriving tokens are cancelled by anti-tokens

Branch target

address

PC+4

No branch

Take branch

Example: mux for next-PC calculation

Elastic circuits


How to implement anti-tokens ?

Valid+

Valid+

Valid+

+

Stop+

Stop+

-

Valid–

Valid–

Stop–

Stop–

Elastic circuits


Dual elastic controllers

En

En

+

+

V

V

+

+

S

S

-

-

V

V

-

-

S

S

Elastic circuits


Fork/join

Dual fork/join

Join with early evaluation

Elastic circuits


Re-designing for average performance

F

Fslow

Early evaluation

Ffast

slow / fast

Elastic circuits


H.264 CABAC decoder

Gotmanov, Kishinevsky and Galceran-OmsEvaluation of flexible latencies: designing synchronous elastic H.264 CABAC decoder

Proc. Problems in design of micro- and nano-electronic systems

Moscow, Oct. 2010 (in Russian)

Elastic circuits


Profiling

Elastic circuits


H.264 CABAC decoder

Elastic circuits


Area vs. Performance

Area

Effective Cycle Time

Elastic circuits


Conclusions

  • Rigid systems preserve timing equivalence(data always valid at every cycle)

  • Elastic systems waive timing equivalence to enablemore concurrency

    (bubbles decrease throughput, but reduce cycle time)

  • A new avenue of performance optimizations can emerge to build correct-by-construction pipelines

Θ

Θ

Elastic circuits


Unifying sync/async elasticity

  • J. Carmona, J. Cortadella,M. Kishinevskyand A. Taubin,Elastic Circuits,IEEE Trans. On CAD, Oct. 2009.

Elastic circuits


Be elastic …

Elastic circuits


  • Login