Elastic circuits blending synchronous and asynchronous technologies
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Elastic Circuits blending synchronous and asynchronous technologies. Jordi Cortadella Universitat Politècnica de Catalunya, Barcelona (joint work with M. Kishinevsky and M. Galceran-Oms ) Collège de France May 21 st , 2013. … t ime is elastic …. S ynchronous circuit. Flip Flops.

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Elastic circuits blending synchronous and asynchronous technologies

Elastic Circuitsblending synchronous and asynchronous technologies

Jordi Cortadella

Universitat Politècnica de Catalunya, Barcelona

(joint work with M. Kishinevsky and M. Galceran-Oms)

Collège de FranceMay 21st, 2013


Elastic circuits blending synchronous and asynchronous technologies

… time is elastic …

Elastic circuits


S ynchronous circuit

Synchronous circuit

Flip Flops

CombinationalLogic

Flip Flops

PLL

Elastic circuits


Asynchronous circuit

Asynchronous circuit

L

CombinationalLogic

L

C

C

delay

4-phase

Elastic circuits


Asynchronous circuit1

Asynchronous circuit

ReqIn

ReqOut

C

C

C

C

AckOut

AckIn

  • David Muller’s pipeline (late 50’s)

  • Sutherland’s Micropipelines (Turing award, 1989)

Elastic circuits


Globally asynchronous locally synchronous

Globally-asynchronousLocally-synchronous

GALS


Soc design with gals

SoC design with GALS

  • Most IPs are synchronous

  • Different components may have different operating frequencies

  • Some components have variable latencies (e.g., cache hit/miss latency)

  • Multiple clock domains are essential

DSP

P

CLK3

Bridge

Bridge

CDC

CDC

Fast Bus

CLK1

Mem

CLK2

Slow Bus

Elastic circuits


Multiple clock domains

Multiple clock domains

Independent clocks

Rational clockfrequencies

Single clock(mesochronous)

CLK1

f1/f0

CLK

(f0)

f2/f0

CLK2

CLK0

CLK

f3/f0

CLK3

(controllable skew)

Elastic circuits


Synchronous handshakes

Synchronous handshakes

Sender

Receiver

Data

Valid

Ack

CLK1

CLK2

  • The arrival of data is unpredictable

  • Handshakes solve the problem

Elastic circuits


The problem metastability

The problem: metastability

D

Q

D

Q

CLKS

CLKR

setup

hold

CLKR

D

Q

?

Elastic circuits


Metastability

Metastability

Source: W. J. Dally, Lecture notes for EE108A, Lecture 13.Metastability and Synchronization Failure (or When Good Flip-Flops go Bad) 11/9/2005.

Elastic circuits


Metastability1

Metastability

logic 0

logic 1

metastable

Elastic circuits


Classical synchronous solution

Classical synchronous solution

D

Q

D

Q

D

Q

D

Q

CLKT

CLKR

Mean Time Between Failures

fФ:frequency of the clock

fD:frequency of the data

tr:resolve time available

W:metastability window

:resolve time constant

Example

Elastic circuits


Handshake with synchronizers

Handshake with synchronizers

Sender

Receiver

Data

Valid

Ack

CLK1

CLK2

  • Simple solution

  • Throughput can be highly degraded:a long round trip for every transaction

Elastic circuits


Asynchronous fifos

Asynchronous FIFOs

Circular buffer

Data

Data

3-4 cycles

1 cycle

1 cycle

Valid

Valid

FIFO control

Ack

Ack

Clk Out

Clk In

  • Ack is issued as soon as data has been delivered

  • No impact on throughput (1 token/cycle)

  • Min latency determined by the internal synchronizers

  • Some tricky structures for the FIFO pointers (e.g. Grey encoding)

Elastic circuits


Soc design with gals1

SoC design with GALS

  • Bridges for Clock Domain Crossing usually contain asynchronous FIFOs

  • Latency cost only when interfacing with synchronous domains

  • No latency penalty between asynchronous domains

DSP

P

CLK3

Bridge

Bridge

CDC

CDC

Fast Bus

CLK1

Mem

CLK2

Slow Bus

Elastic circuits


Synchronous and asynchronous meeting each other

Synchronous and Asynchronousmeeting each other


Meanwhile a small village of indomitable engineers was resisting the synchronous occupation

Meanwhile, a small village ofindomitable engineers was resisting the synchronous occupation …

Asynchronia

Elastic circuits


Elastic circuits blending synchronous and asynchronous technologies

Bill Grundmann(Intel’s director of CAD research,

Technical director for CAD technology for the Alpha Microprocessor):

“The specification of a complex system is usuallyasynchronous (functional units, messages, queues, …),

… however the clock appears when we move downto the implementation levels”

(in a technical discussion about system designwithM. Kishinevskyand J. Cortadella, 2004)

Elastic circuits


Async and sync meeting each other

Async and Sync meeting each other

Async

  • Modular (time elasticity)

  • But hard to analyze and synthesize

J. O’Leary and G. Brown, 1997Synchronous emulation of asynchronous circuits

A. Peetersand K. Van Berkel, 2001

Synchronous handshake circuits

Elastic Circuits(Sync / Async)

Cortadella et al., Desynchronization, 2003

L. Carloni et al., 1999A methodology for correct-by-construction latency-insensitive design

  • Easy to analyze and synthesize

  • Not modular (time rigid)

Sync

Elastic circuits


Different flavors of elasticity

Different flavors of elasticity

+

Rigid

4

7

1

4

8

3

time

0

1

2

4

+

7

1

a

3

4

8

0

1

2

Asynchronous

7

1

4

1

2

0

+

e

8

4

3

Synchronous Elastic

Elastic circuits


Why synchronous elasticity

Why synchronous elasticity?

  • Time is discrete (cycle based), but unpredictable (unknown number of cycles)

  • Examples

    • Short/long integer addition (8 bits, 64 bits)

    • Floating-point units

    • Cache latency: fast hit(2), slow hit(3), miss(>20)

    • Bus arbitration

    • Latencies in Network-on-Chip

    • … and many others

Elastic circuits


Even at design time

… even at design time

Sender

Receiver

CLK

Can we add a register without modifying the functionality of the system?

Elastic circuits


Many systems are already elastic

Many systems are already elastic

AMBA AXI bus protocol

Handshake signals

Elastic circuits


Designing with synchronous elasticity

Designing withsynchronous elasticity


Communication channel

Communication channel

sender

receiver

Data

Data

Long wires: slow transmission

Elastic circuits


Pipelined communication

Pipelined communication

Data

sender

receiver

Data

How about if the sender does not always send valid data?

Elastic circuits


Pipelined communication1

Pipelined communication

Data

sender

receiver

Data

Elastic circuits


Pipelined communication2

Pipelined communication

Data

sender

receiver

Data

Elastic circuits


Pipelined communication3

Pipelined communication

Data

sender

receiver

Data

Elastic circuits


Pipelined communication4

Pipelined communication

Data

sender

receiver

Data

???

Elastic circuits


The valid bit

The Valid bit

sender

receiver

Data

Data

Valid

Valid

Elastic circuits


The valid bit1

The Valid bit

Data

Valid

sender

receiver

Data

Valid

Elastic circuits


The valid bit2

The Valid bit

Data

Valid

sender

receiver

Data

Valid

Elastic circuits


The valid bit3

The Valid bit

Data

Valid

sender

receiver

Data

Valid

Elastic circuits


The valid bit4

The Valid bit

Data

Valid

sender

receiver

Data

Valid

How about if the receiver is not always ready ?

Elastic circuits


The stop bit

The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

0

0

Elastic circuits


The stop bit1

The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

1

1

Elastic circuits


The stop bit2

The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

1

1

1

Elastic circuits


The stop bit3

The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

1

1

1

1

1

Back-pressure

Elastic circuits


The stop bit4

The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

1

1

1

1

0

Elastic circuits


The stop bit5

The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

0

0

Elastic circuits


The stop bit6

The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

0

0

Elastic circuits


The stop bit7

The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

0

0

Elastic circuits


The stop bit8

The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

0

0

Elastic circuits


The stop bit9

The Stop bit

sender

receiver

Data

Data

Valid

Valid

Stop

Stop

0

0

0

0

1

Long combinational path

Elastic circuits


R elay stations carloni 1999

Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations carloni 1999

Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations carloni 19991

Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations carloni 19992

Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations carloni 19993

Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations carloni 19994

Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations carloni 19995

Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations carloni 19996

Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations carloni 19997

Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

Elastic circuits


Relay stations carloni 19998

Relay stations (Carloni, 1999)

sender

receiver

shell

shell

main

main

main

pearl

pearl

aux

aux

aux

  • Handshakes with short wires

  • Double storage required

Elastic circuits


Flip flops vs latches

Flip-flops vs. latches

sender

receiver

FF

FF

1 cycle

Elastic circuits


Flip flops vs latches1

Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Elastic circuits


Flip flops vs latches2

Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Elastic circuits


Flip flops vs latches3

Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Elastic circuits


Flip flops vs latches4

Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Elastic circuits


Flip flops vs latches5

Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Elastic circuits


Flip flops vs latches6

Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Elastic circuits


Flip flops vs latches7

Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Flip-flops already have a

double storage capability, but …

Elastic circuits


Flip flops vs latches8

Flip-flops vs. latches

sender

receiver

H

L

H

L

1 cycle

Not allowed in conventional

FF-based design !

Elastic circuits


Flip flops vs latches9

Flip-flops vs. latches

H

L

H

L

sender

receiver

1 cycle

Let’s make the master/slave latches independent

Elastic circuits


Flip flops vs latches10

Flip-flops vs. latches

H

L

H

L

sender

receiver

½ cycle

½ cycle

Let’s make the master/slave latches independent

Only half of the latches (H or L) can move tokens

Elastic circuits


Synchronous elasticity

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

Valid

Valid

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity1

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity2

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity3

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity4

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity5

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity6

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

0

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity7

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

0

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity8

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

0

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity9

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

0

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity10

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

0

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity11

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity12

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity13

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity14

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity15

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity16

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity17

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity18

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity19

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

1

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity20

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity21

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity22

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity23

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity24

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity25

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity26

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Synchronous elasticity27

Synchronous elasticity

sender

receiver

Data

Data

En

En

En

En

V

V

V

V

1

Valid

Valid

0

Stop

Stop

S

S

S

S

Elastic circuits


Basic vs block

Basic VS block

Eni

Eni

Vi-1

Vi

Vi-1

Vi

VS

Si-1

Si

Si-1

Si

Elastic circuits


Elastic netlists

Elastic netlists

Enable signal

to data latches

V

S

VS

Fork

V

S

Join

VS

Join / Fork

VS

V

S

V

S

VS

Elastic circuits


Elastic circuits blending synchronous and asynchronous technologies

Join

+

V1

VS

V

VS

S1

VS

S

V2

VS

VS

S2

Elastic circuits


Lazy fork

Lazy Fork

V

V1

S1

V2

S

S2

Elastic circuits


Eager fork

Eager Fork

S1

^

V1

V

V2

^

S

S2

Elastic circuits


Variable latency units

Variable Latency Units

V/S

V/S

[0 - k] cycles

done

clear

go

Elastic circuits


Design automation

Design automation


Transforming sync into elastic

Transforming sync into elastic

Elastic circuits


Transforming sync into elastic1

Transforming sync into elastic

Elastic circuits


Transforming sync into elastic2

Transforming sync into elastic

Behavioralequivalenceis preserved

Elastic circuits


Elastic esterel

Elastic Esterel

module ABRO:

input A,B,R;

output O;

loop

[ await A || await B ];

emit O

each R

end module

Marc GalceranOms, Master thesis, 2007

Elastic circuits


Elastic esterel1

Elastic Esterel

A

PauseReg7

R

O

Boot

B

PauseReg11

Elastic circuits


Elastic esterel2

Elastic Esterel

A

PauseReg7

R

O

Boot

B

PauseReg11

Elastic Control Layer

Valid_A

Stop_A

Valid_B

Valid_O

Stop_B

Stop_O

Valid_R

Stop_R

Elastic circuits


Circuit vs architectural cycles

Circuit vs. μarchitectural cycles

Elastic circuits


Synchronous handshake circuits peeters 2001

Synchronous handshake circuits (Peeters, 2001)

int = type [0..255]& gcd: main proc(in? chan <<int,int>> & out! chanint)begin x, y: varint| forever do in?<<x,y>> ; do x <> y thenif x < y then y:=y-xelse x:=x-yfiod ; out!xodend

Sources:

J. Kessels and A. Peeters.DESCALE: A Design Experiment for a SmartCard Application Consuming Low Energy,in Principles of Asynchronous Circuit Design, A Systems Perspective,Eds., J. Sparso and S. Furber, Kluwer Academic Publishers, 2001.

P.A.Beerel, R.O. Ozdag and M. Ferretti.A Designer’s Guide to Asynchronous VLSI,Cambridge University Press, 2010.

Elastic circuits


Generalization bounded fifos

Generalization: bounded FIFOs

Out

In

B3

B1

B2

Bounded Dataflow Networks

Elastic circuits


Behavioral equivalence

Behavioral equivalence

Synchronous:

D: a b c d e f g h i j k …

Elastic:

D: a a b bb c d e e f g g h iii j k …

V: 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 …

Elastic circuits


Early evaluation

Early evaluation


Early evaluation1

Early evaluation

3

x

15

2

5

Elastic circuits


Early evaluation2

Early evaluation

3

x

6

2

Elastic circuits


Early evaluation3

Early evaluation

0

x

0

8

Elastic circuits


Early evaluation4

Early evaluation

  • Only wait for required inputs

  • Late arriving tokens are cancelled by anti-tokens

Branch target

address

PC+4

No branch

Take branch

Example: mux for next-PC calculation

Elastic circuits


How to implement anti tokens

How to implement anti-tokens ?

Valid+

Valid+

Valid+

+

Stop+

Stop+

-

Valid–

Valid–

Stop–

Stop–

Elastic circuits


Dual elastic controllers

Dual elastic controllers

En

En

+

+

V

V

+

+

S

S

-

-

V

V

-

-

S

S

Elastic circuits


Fork join

Fork/join

Dual fork/join

Join with early evaluation

Elastic circuits


Re designing for average performance

Re-designing for average performance

F

Fslow

Early evaluation

Ffast

slow / fast

Elastic circuits


H 264 cabac decoder

H.264 CABAC decoder

Gotmanov, Kishinevsky and Galceran-OmsEvaluation of flexible latencies: designing synchronous elastic H.264 CABAC decoder

Proc. Problems in design of micro- and nano-electronic systems

Moscow, Oct. 2010 (in Russian)

Elastic circuits


Profiling

Profiling

Elastic circuits


H 264 cabac decoder1

H.264 CABAC decoder

Elastic circuits


Area vs performance

Area vs. Performance

Area

Effective Cycle Time

Elastic circuits


Conclusions

Conclusions

  • Rigid systems preserve timing equivalence(data always valid at every cycle)

  • Elastic systems waive timing equivalence to enablemore concurrency

    (bubbles decrease throughput, but reduce cycle time)

  • A new avenue of performance optimizations can emerge to build correct-by-construction pipelines

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Elastic circuits


Unifying sync async elasticity

Unifying sync/async elasticity

  • J. Carmona, J. Cortadella,M. Kishinevskyand A. Taubin,Elastic Circuits,IEEE Trans. On CAD, Oct. 2009.

Elastic circuits


Elastic circuits blending synchronous and asynchronous technologies

Be elastic …

Elastic circuits


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