Power pulsing schemes for analog and digital electronics of the vertex detectors at CLIC
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Power pulsing schemes for analog and digital electronics of the vertex detectors at CLIC. Authors:. Cristian Alejandro Fuentes Rojas , PH-ESE-FE, CERN Georges Blanchot, PH-ESE-FE, CERN Dominik Dannheim, PH-LCD, CERN. TWEPP 2013, September 25th. [email protected]

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Power pulsing schemes for analog and digital electronics of the vertex detectors at CLIC

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Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Power pulsing schemes for analog and digital electronics of the vertex detectors at CLIC

Authors:

Cristian Alejandro Fuentes Rojas,PH-ESE-FE, CERN

Georges Blanchot, PH-ESE-FE, CERN

Dominik Dannheim, PH-LCD, CERN

TWEPP 2013, September 25th

[email protected]


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

CLIC_ILD inner tracking region

Ladder

Power in

Power in

24 cm

1 cm

CLICpix

Vertex barrel

1 cm

The ladder is formed by 24 readout ASICs (CLICpix)

Half a ladder, as we power from both sides

Ladders

CLIC detector, Vertex barrel, ladder & CLICpix

CLIC: Compact Linear Collider

Detector


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Restrictions for powering

1) Material Budget: < 0.2%X0 for a detection layer, from which 0.1 %X0 is already taken by the silicon sensor + readout chip. (100 µm of silicon). This leaves, therefore, less than 0.1%X0 for cooling, powering and mechanical structures.

2) Low losses: < 50 mW/cm2 in the sensor area, as the heat-removal solution is based on air-cooling to reduce mass.

3) High magnetic Field:4 to 5 [Tesla] restricting the use of ferromagnetic material.

extra challenge for analog electronics

4) Regulation:within 5% (60 mV) on the ASIC during the acquisition time in order to have a correct ToT measurement. (CLICPIX specifications).

Note: Radiation is not a concern


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Digital Chip [1]

Digital Chip [2]

Read Out

Read Out

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

OFF

2 W/cm2

100 mW/cm2

Idle

Idle

360 mW/cm2

8 mW/cm2

Turned OFF

OFF

Idle

Idle

Idle

Read Out

20/13 ms

20/13 ms

Idle

Read Out

Idle

Digital Chip [12]

20/13 ms

Power consumption of Half a Ladder

Train Bunch

20µs

20µs

Analog Chip [1:12]

  • Analog electronics can be turned OFF (power pulsing) to reduce the average power consumption (2m W/cm2 instead of 2 W/cm2 if it was ON all the time)

  • One chip is readout every 20/13 ms. The time the chip needs to be read out depends on the occupancy, which maximum is 3% ( 300 µs). Avg power consumption= 13m W/cm2

  • Analog voltage is 1.2V while the digital is expected to be 1V.

  • In order to fulfill the regulation restriction, the chip is turned ON by parts. That allows to have a current rise time of around 1us. (next slide)

Analog and Digital will be powered separately. In that way, their powering schemes could be optimized independently to achieve the requirements from previous slide.


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Small capacitors close to each ASIC at the FE: (10 μF)

✔ The current loop is very small.

Powering half a ladder (analog) (1)

20 A

~20 µs

~1 µs

~1 µs

✖ But there’s need of regulation, as the capacitor discharges when the load is active.

Low dropout (LDO) voltage regulators added per ASIC:

The regulation in the ASIC is achieved, but the input capacitor still discharges..

How do we charge it back to its level to be ready for the next cycle?

DCDC converter option: (Reported last TWEPP 2012)

✔ Its feedback loop charges up the capacitors to the required level.(easy implementation)

✖ Introduces not negligible amount of mass, too high for this particular application.

✖ Current peaks while charging the capacitor. (and it doesn’t use the whole idle time)


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Powering half a ladder (analog) (2)

How do we charge it back to its level to be ready for the next cycle?

...second approach.

Controlled current source at the back-end: (Presented this TWEPP 2013)

Simpler idea behind,

but more difficult to implement.

An estimation of the current at the BE, using the whole period to charge the capacitor, is:

✔Cables from the back-end to the capacitors @ FE can be really light in terms of mass.

From now on, this presentation will refer to this approach.


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

In order to work, the following condition has to be fulfilled:

Principle and waveforms of the scheme

Iin= f ( Vin , t , Vnominal)


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Dummy load: Mosfet + resistor

Two layers Aluminium Flex Cable

1mm wide, 20μm thick/layer

Power storage and regulation:

input Si cap (3 x 3.3 μF) + LDO (out: 1.2V) + output Si cap (1μF)

Evaluation using Analog Dummy Load

The CLICpix is being developed, so in order to test the scheme we need a dummy load.

This duplicates 12 times, representing the 12 ASICs, the power storage, regulation and cabling.

3 x 3.3 μF

1μF


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Why aluminium cables?

For the same resistance than a copper cable, aluminium cables have around 4 times lower material contribution. The aluminium flex cables were made at the CERN PCB shop.

Why silicon capacitors?

Low mass and flat. They can have a thickness down to 80 μm.

Ceramic capacitor of small smd package (0402 or 0201) can have comparable material. Nevertheless, their capacitance change dramatically (more than 80% of their value for some conditions) with the voltage applied (Vbias), making them impractical for our application.

IPDiA company can integrate all the necessary passive components into a single die

Which can be afterwards connected to the CLICpix chip using TSVs

(Through Silicon Vias).

This is just a preliminary idea, and might be explored in the following months.


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Al Flex Cable

Dummy load

Back-end cables

Back-end cables

Dummy load/ test board

Al Flex Cable

Controlled current source

Controlled current source

Implementation @ Lab


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Regulation during ton < 20 mV (analog)

Vload

1.2 V

∆V = 16 mV

2 A per chip

5.3 V

VCap

Iload for 1 ASIC

Particular case ton = 20μs

1.4 V

Voltage drop < 20 mV

Measured average Power consumption < 10 mW/cm2

✔ 16 mV

voltage drop


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Digital Dummy Load / test board


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Al Flex Cable

Back-end cables

Dummy load

Dummy load/ test board

Back-end cables

Al Flex Cable

Controlled current source

Controlled current source

Implementation @ Lab


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Digital results

Vload

1.2 V

∆V = 70 mV

360 mA

IBE

Iload for 1 ASIC

180 mV

100 mA

8 mA

3 V

VCap

1.8 V

20 ms

Voltage drop < 70 mV (140mV peak-peak)

Measured average Power consumption < 35 mW/cm2

For 300 µs of reading time


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Material Budget Today

Silicon capacitors (today 25 μF/cm2):

Analog

+

Digital

=

Total

Flex cable

LDO

Flex cable

LDO

Flex cable

LDO

+

=

Si cap

Si cap

Si cap

+

=

0.064 % X0

0.04 % X0

0.104 % X0


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Flex cable

Flex cable

Flex cable

LDO

LDO

LDO

Si cap

Si cap

Si cap

Material Budget Today Tomorrow*

Silicon capacitors (today 25 100 μF/cm2):

Analog

+

Digital

=

Total

+

=

+

=

0.028 % X0

0.015 % X0

0.043 % X0

Flex cable & LDO contribution now is half of the total.

  • LDOs will be tried to be included in CLICPix

  • Flex cable material can easily be decreased. (We will produce a new al Flex)

* for IPDiA roadmap and reference, see back-up slides


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Conclusions

During this talk we presented a power-pulsing scheme to power the analog and digital electronics of the future vertex barrel read-out ASIC CLICpix.

The presented scheme counted with regulation and silicon capacitors in the front-end, which were charged up using a back-end current supply of less than 50 mA for the analog part and less than 200mA for the digital one.

Some of the achieved results were:

  • Good regulation as required:

    • Analog voltage drop < 20 mV and Digital voltage drop < 70 mV

  • Total Power losses/dissipation < 50mW/cm2 as required.

    • Analog < 10mW/cm2 and Digital < 35mW/cm2

  • Small current (20mA to 60mA for Analog and 100mA to 200mA for Digital ) through the whole cable depending on the load consumption. => Low material cables.

  • Today’s Material Budget of 0.104 % X0, which is expected to be less than 0.043 % X0. (after improvements of silicon capacitors technology).

  • We expect to decrease this contribution furthermore by redesigning the aluminum flex cable and by integrating the LDOs in the CLICPix ASIC.


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Thanks for your attention :)


Back up slides

BACK-UP Slides


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

IPDiA Roadmap

IPD low profile roadmap

Low Profile Integrated Passive Devices with 3D High Density Capacitors Ideal for Embedded and Die Stacking Solutions

URL:

http://www.ipdia.com/download.php?file=%2Fproducts%2FESTC2012.pdf&cat=publications


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Measurements for same load value (analog)

Iload for 1 ASIC

Vload

1.2 V

2 A

Vcap

5.3 V

0 A

IBE

1.4 V

22 mA

0 V

IBE is constant. Around 22 mA


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Change in the load consumption (analog)

Iload for 1 ASIC

Vload

1.2 V

2 A

Vcap

5.3 V

0 A

IBE

22 mA

2.1 V

1.4 V

0 V

IBE is variable. Around 22 mA


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

En/Dis voltage regulator (analog)

1.2 V

Vcap

5.3 V

2 A

Iload for 1 ASIC

0 A

1.4 V

Vload

0 V


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Big C

Small C

Big ∆I/∆t

Big ∆V/∆t

(far from FE)

Frequency spectrum difference (a)


Power pulsing schemes for analog and digital electronics of the vertex detectors at clic

Frequency spectrum difference (b)


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