Assembly Language for Intel-Based Computers

1. Assembly Language for Intel-Based Computers Kip Irvine Chapter 2: IA-32 Processor Architecture

2. General Concepts • Basic microcomputer design • Instruction execution cycle • Reading from memory Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

3. Basic Microcomputer Design • clock synchronizes CPU operations • control unit (CU) coordinates sequence of execution steps • ALU performs arithmetic and bitwise processing Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

4. Clock • synchronizes all CPU and BUS operations • machine (clock) cycle measures time of a single operation • clock is used to trigger events Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

5. Instruction Execution Cycle • Fetch • Decode • Fetch operands • Execute • Store output Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

6. Multi-Stage Pipeline • Instruction execution divided into discrete stages Example of a non-pipelined processor. Many wasted cycles. Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

7. Pipelined Execution • More efficient use of cycles, greater throughput of instructions: For k states and n instructions, the number of required cycles is: k + (n – 1) Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

8. Reading from Memory • Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are: • address placed on address bus • Read Line (RD) set low • CPU waits one cycle for memory to respond • Read Line (RD) goes to 1, indicating that the data is on the data bus Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

9. Basic Execution Environment • Addressable memory • General-purpose registers • Index and base registers • Specialized register uses • Status flags • Floating-point Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

10. General-Purpose Registers Named storage locations inside the CPU, optimized for speed. Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

11. Accessing Parts of Registers • Use 8-bit name, 16-bit name, or 32-bit name • Applies to EAX, EBX, ECX, and EDX Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

12. Index and Base Registers • Some registers have only a 16-bit name for their lower half: Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

13. Some Specialized Register Uses (1 of 2) • General-Purpose • EAX – accumulator • ECX – loop counter • ESP – stack pointer • ESI, EDI – index registers • EBP – extended frame pointer • Segment • CS – code segment • DS – data segment • SS – stack segment • ES, FS, GS - additional segments Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

14. Some Specialized Register Uses (2 of 2) • EIP – instruction pointer • EFLAGS • status and control flags • each flag is a single binary bit Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

15. Status Flags • Carry • unsigned arithmetic out of range • Overflow • signed arithmetic out of range • Sign • result is negative • Zero • result is zero • Auxiliary Carry • carry from bit 3 to bit 4 • Parity • sum of 1 bits is an even number Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

16. Carry and Overflow Carry is important when … Adding or subtracting unsigned integers Indicates that the unsigned sum is out of range Overflow is important when … Adding or subtracting signed integers Indicates that the signed sum is out of range Overflow occurs when Adding two positive numbers and the sum is negative Adding two negative numbers and the sum is positive Can happen because of the fixed number of sum bits Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

17. We can have carry without overflow and vice-versa Four cases are possible Carry and Overflow Examples 1 1 1 1 1 218 (-38) 15 79 0 1 0 0 1 1 0 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 0 1 + + + 0 0 1 1 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 1 0 157 (-99) 8 64 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 23 119 143 (-113) Carry = 1 Overflow = 1 Carry = 0 Overflow = 1 Carry = 0 Overflow = 0 1 1 1 1 1 15 0 0 0 0 1 1 1 1 + 1 1 1 1 0 1 0 1 245 (-11) 1 0 0 0 0 0 1 0 0 4 Carry = 1 Overflow = 0 Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

18. Addressable Memory • Protected mode • 4 GB • 32-bit address • Real-address and Virtual-8086 modes • 1 MB space • 20-bit address Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

19. Real-Address mode • 1 MB RAM maximum addressable • Application programs can access any area of memory • Single tasking • Supported by MS-DOS operating system Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

20. Segmented Memory Segmented memory addressing: absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset one segment linear addresses Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

21. Calculating Linear Addresses • Given a segment address, multiply it by 16 (add a hexadecimal zero), and add it to the offset • Example: convert 08F1:0100 to a linear address Adjusted Segment value: 0 8 F 1 0 Add the offset: 0 1 0 0 Linear address: 0 9 0 1 0 Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

22. Calculating Linear Addresses What linear address corresponds to the segment/offset address 028F:0030? 028F0 + 0030 = 02920 Always use hexadecimal notation for addresses. Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

23. Calculating Linear Addresses What segment addresses correspond to the linear address 28F30h? Many different segment-offset addresses can produce the linear address 28F30h. For example: 28F0:0030, 28F3:0000, 28B0:0430, . . . Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

24. Intel Registers Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.