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On Rewiring and Simplification for Canonicity in Threshold Logic CircuitsPowerPoint Presentation

On Rewiring and Simplification for Canonicity in Threshold Logic Circuits

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On Rewiring and Simplification for Canonicity in Threshold Logic Circuits

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On Rewiring and Simplification for Canonicity in Threshold Logic Circuits

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Speaker: Pin-Yi Kuo

Advisor: Chun-Yao Wang

2011/5/20

On Rewiring and Simplification for Canonicity in Threshold Logic Circuits

- Rectification
- Critical-effect

- Introduction
- Rewiring
- Rewiring flow
- Preliminary
- Preprocess
- Input grouping and gate decomposition

- Target wire removal
- Useless threshold gate
- Useless threshold group
- Critical input
- Useless input

- A linear threshold gate (LTG) is an n binary input and one binary output function defined as below:
y = 1 if

0if

n binary inputs x1, x2, … ,xnwith weights w1, w2, … ,wn

a single binary output y

a threshold value T

x1

x2

xn

w1

w2

wn

T

f

…

…

- A network is composed of LTGs is called a threshold network.
- An example of threshold logic network and its corresponding Boolean representation.

- Every Boolean function has infinitely distinct representations in threshold logic.
- In our work, the threshold logic is generated with ILP-based tools.
- Linear programs are problems that can be expressed in canonical form.

- In our work, the threshold logic is generated with ILP-based tools.
- For convenience, we assume the weights and threshold of a threshold function are positive integers.
- Negative integers can be transformed into positive ones.

- The relationship of the weights and threshold value between functions containing xi in positive and negative phase is given in [1].
- Step 1. Invert the negative weights into positive ones and complement the corresponding variables.
- Step 2. Increase the threshold value by adding the absolute value of the negative weight.

x1

x2

x3

2

1

-1

1

f

x1

x2

y3

2

1

1

2

f

y3 = x3’

[1] S. Muroga. Threshold Logic and its Applications. New York, NY: John Wiley, 1971.

- Combinational equivalence checking
- Rewire on the compared threshold logic networks to keep the appearances of them the same.
- The connectivity among all gates.
- The functionality of each corresponding gate.

- Rewire on the compared threshold logic networks to keep the appearances of them the same.
- Resynthesis
- Generate a threshold network with a new fanin number constraint instead of resynthesizing.

- Rectification
- Critical effect

- Introduction
- Rewiring
- Rewiring flow
- Preliminary
- Preprocess
- Input grouping and gate decomposition

- Target wire removal
- Useless threshold gate
- Useless threshold group
- Critical input
- Useless input

START

Input:

A threshold network and a target wire

Grouping and decomposition

Target wire removal

The target wire is critical?

No

Yes

Rectify at the transitive fanout cone?

No

Case 3

Yes

Case 1

Case 2

- Rectification
- Threshold value change
- Rectification network constructionat each input
- AND connection

- Rectification
- The useless input removal
- Rectification network construction
- OR connection

- Rectification
- Threshold value change
- Rectification network construction
- AND connection

Simplification

Output:

The synthesized threshold network

END

- Input a given threshold logic network, and a target wire to be removed
- Preprocess
- Input grouping and gate decomposition

- The target wire removal
- Rectification network construction
- Preserve the remaining functionality
- Change the threshold value if necessary

- Rectify at different locations
- Search for the rectification network.
- Different connection

- Preserve the remaining functionality
- Output the rewired threshold network

- A threshold logic gate can be divided into many groups.
- Observe the threshold logic gate in groups.

- Objective: Separate the inputs and the corresponding weights into different groups.
- Step 1. Separate an input whose weight is equal to the threshold value of the objective gate as a single group.
- Step 2. The remaining inputs are separated as another group.

a

b

c

d

e

f

3

2

1

1

5

5

5

f

- Each group can be extracted as a new threshold logic gate.
- The threshold value of decomposition gate is the same as that of the objective gate.
- The weights of the objective gate associated with the decomposition gate is the threshold value.

The decomposition gate

a

b

c

a

b

c

d

3

1

1

1

1

1

1

3

3

f

3

d

3

3

f

- Remove the target wire and its corresponding weight from the objective gate directly.
- The outcomes of the objective gate after a removal.
- A useless threshold logic gate.
- A normal threshold logic gate.

- The outcomes of the objective gate after a removal.
- It’s necessary to ensure the objective gate out of uselessness after any operation in our rewiring procedure.

- Def: A single group LTG is useless if and only if it is an empty gate or it outputs zero for all input combinations.
- Lemma: Given a nonempty LTG, it is useless if and only if it satisfies the following equation, where n is the number of inputs in this gate.

The threshold logic gate is useless because it outputs zero for all input combinations.

a

b

c

1

1

1

4

f

- Def: An input in a single group LTG is critical if and only if this LTG will become useless after removing this input.
- Lemma: Given a single group LTG, an input xj with its corresponding weight wj is critical if and only if it satisfies the following equation, where n is the number of inputs in this gate.

Given an LTG, input c is critical because the group will become useless after removing c.

c

d

e

2

1

1

3

f

- Def: An input is useless if and only if the output of this LTG is intact when this input toggles under all input combinations.

The threshold logic input c is useless because the output is intact when input c toggles for all input combinations.

a

b

c

3

2

1

5

f

- Lemma: Given an input xj with its corresponding weight wj, xj is useless if and only if it satisfies either EQ(A) or EQ(B) for each input combination, where n is the number of inputs in this gate.

(A)

and

(B)

and

- Useless gates and useless inputs are not allowed in a threshold network.
- A target wire removal may generate them incidentally.

- A critical input is a necessary input for keeping the LTG out of uselessness.

- The construction of the rectification network varies with the characteristic of the target wire and the rectification location.
- Transitive fanout cone of the objective gate.
- Transitive fanin cone of the objective gate.

- Def: A single group LTG has a critical-effect if and only if there exists an assignment such that the output changes from 1 to 0 when each one of its inputs in this assignment changes from 1 to 0.
- Lemma: Given a single group LTG, the LTG has a critical-effect if it satisfies the following equation, where n is the number of inputs in this gate.

Given an LTG, the LTG has a critical-effect under these vectors (a,b,c,d) = (1,1,0,0) and (1,0,1,1)

a

b

c

d

5

f

3

2

1

1

f

3

- A vector where a gate has a critical-effect is called a critical-effect vector.
- The value of the target wire in the critical-effect vector determine whether or not a subfunction is lost after removing the target wire.

a

b

c

2

1

1

for the target wire b

- Case 1: The target wire is not critical:
- The remaining objective gate will not become useless.
- Keep the threshold value.
- Search for the rectification network with critical-effect.

- Since adding the rectification network at the transitive fanin cone will affect the remaining functionality among other inputs, we only add the rectification network at the transitive fanout cone of the objective gate.

- The remaining objective gate will not become useless.

- Given a single group LTG and the target wire xa.
- Step 1: Remove any useless input.
- Step 2:Get all critical-effect vectors where xa=1.
- Step 3: Collect all inputs that are assumed to be 1 in these critical-effect vectors

a

b

c

d

e

5

2

1

1

1

7

f

The critical-effect vectors

The objective gate and the target wire d.

Inputs a,dand e are found in the critical effect vector 10011.

Inputs a,c and d are found in the critical effect vector 10110.

- Step 4: Get the rectification network by creating a new gate consisting of the inputs found in step 3 with its corresponding weight and threshold value of the objective gate.
- Step 5: Connect the remaining objective gate to this rectification network with an OR gate at its transitive fanout cone.

n1

n2

a

b

c

e

a

c

d

e

a

c

d

e

a

b

c

e

1

1

5

1

1

1

5

2

1

1

5

2

1

1

5

1

1

1

1

7

7

7

7

f

n2

n1

The remaining objective gate

The rectification network

- Case 2: The target wire is critical, and we rectify it at the transitive fanout cone:
- It will cause a useless gate after the removal.
- Prevent a useless gate generation.

- It will cause a useless gate after the removal.
- Given a single group LTG and the target wire xa.
- Step 1: Decrease the threshold value in the remaining objective gate by wa.
- Step 2: The rectification network is the target wire only.
- Step 3: Connect the remaining objective gate to this rectification network with an AND gate at its transitive fanout cone.

f

n1

10

4

- Given a single group LTG and the target wire xa.

y

b

c

d

e

b

c

d

e

a

b

c

d

e

4

3

1

1

4

3

1

1

6

4

3

1

1

The given LTG and the target wire a

The remaining objective gate

a

n1

1

1

2

4

- Case 3: The target wire is critical, and we rectify it at the transitive fanin cone:
- It will cause a useless gate after the removal.
- Prevent a useless gate generation.

- It will cause a useless gate after the removal.
- Given a single group LTG and the target wire xa.
- Step 1: Decrease the threshold value in the remaining objective gate by wa.
- Step 2: The rectification network is the target wire only.
- Step 3: Connect this rectification network to each input of the remaining objective gate with an AND gate at its transitive fanin cones.

2

2

2

2

4

1

1

1

1

4

3

1

1

1

1

1

1

f

f

n1

4

10

- Given a single group LTG and the target wire a

b

c

d

e

a

b

c

d

e

4

3

1

1

6

4

3

1

1

a

b

a

c

The given LTG and the target wire a

a

d

a

e

The remaining objective gate

- Rewire any target wire in a threshold network without variation of functionality.
- It only depends on the information of input and weight and the threshold value of each gate without the Boolean representations.

- Rectification
- Critical effect

- Introduction
- Rewiring
- Rewiring flow
- Preliminary
- Preprocess
- Input grouping and gate decomposition

- Target wire removal
- Useless threshold gate
- Useless threshold group
- Critical input
- Useless input

- After the synthesis, the ILP solver will give a canonical solution for the weight and threshold value of each threshold logic gate.
- In our rewiring procedure, some threshold gates will not be represented canonically.
- Keep each threshold logic gate simplified after each removal and rectification procedure.
- Minimum positive weight

- Keep each threshold logic gate simplified after each removal and rectification procedure.

START

Decrease the input weight and the threshold value sequentially

Input

A given LTG

Check the validity of this decrement

No

Divide the LTG by

a common divisor

Yes

Get the critical-effect vectors and their brothervectors

Update the LTGand divide the LTG by a common divisor

There exists an input

weight to decrease?

Yes

No

Output

The canonical LTG

END

- A Subvector of a vector is a vector whose input assumed to be 1 is the proper subset of this vector.
- A Supervector of a vector is a vector whose input assumed to be 1 is the proper superset of this vector.
- A Brothervector of a vector is a vector which has the same number of inputs assumed to be 1 as this vector.

A vector (a, b, c) = (0, 1, 1)

Subvectors: (0, 0, 1) and (0, 1, 0)

Supervector: (1, 1, 1)

Brothervectors: (1, 0, 1) and (1, 1, 0)

a

b

c

d

a

b

c

d

a

b

c

d

9

9

4

4

6

8

2

2

3

4

2

2

3

4

f

f

f

- Given a single group LTG.
- Step 1: Ensure that the weights for all inputs and threshold value have no common divisor which is larger than 1.
- The LTG is necessary to be divided by a common divisor.

- Step 2: Keep the critical-effect vectors and the brothervector of all critical-effect vectors.
- Record the outputs of the gate under these input assignment set.

- Step 1: Ensure that the weights for all inputs and threshold value have no common divisor which is larger than 1.

18

a

b

c

d

a

b

c

d

9

8

2

2

3

4

1

1

3

4

f

f

- Step 3: Iteratively decrease each input weight and the threshold value. Get the new representation after the weight-decreasing operation.
- If we decrease a unique weight by 1 in an LTG, the threshold value is decreased by 1 as well.
- The inputs with the same weight must be decreased at the same time.
- The threshold value is decreased by the number of 1 in these same weight inputs of any critical-effect vectors.

The LTG before the simplification

The LTG after the same-weight inputs decreasing

a

b

c

d

a

b

c

d

9

8

2

2

3

4

1

1

3

4

f

f

- Theorem: Given two single group LTGs, they are functionally equivalent if and only if they produce the same outputs under all critical-effect vectors and the brothervectors of all critical-effect vectors.

- Step 4: Verify if the functionality between the original LTG and the new LTG intact or not after each weight-decreasing operation.
- Step 4-a: If an inconsistency occurs, the weight-decreasing operation is invalid.
- Keep the original threshold logic gate.
- The input cannot be decreased in this iteration.

- Step 4-b: If all outputs are the same, the weight-decreasing operation is valid.
- Obtain a new representation.
- Ensure that the weights for all inputs and threshold value have common divisor 1.

- Step 4-a: If an inconsistency occurs, the weight-decreasing operation is invalid.

- Step 5: End the simplification procedure if any weight-decreasing operation is invalid. Or return to step 3.

a

b

c

d

a

b

c

d

a

b

c

d

a

b

c

d

a

b

c

d

a

b

c

d

5

7

3

6

8

5

1

1

2

3

1

1

1

1

1

1

2

4

1

1

2

2

1

1

3

4

1

1

1

3

f

f

f

f

f

f

Decrease the weight in input c

Decrease the weight in input d

Decrease the weight in input c

Decrease the weight in input d

Decrease the weights in inputs c, d

Invalid

Invalid

- The LTGs with the same functionality will have the same appearance after the simplification procedure.
- It depends only on weights of the inputs and threshold value information of an LTG.
- We use fewer input assignments to verify the functionality between the compared gates instead of all input combinations.

- Rectification
- Critical effect

- Introduction
- Rewiring
- Rewiring flow
- Preliminary
- Preprocess
- Input grouping and gate decomposition

- Target wire removal
- Useless threshold gate
- Useless threshold group
- Critical input
- Useless input

- The experiment consists of two parts.
- The capability of logic restructuring.
- Randomly select an input from each gate as a target wire.
- Simplify on changed LTGs.

- Resynthesize a threshold network with a new fanin number constraint compared to [2] .
- Randomly select an input from the gate violating the fanin number constraint as a target wire.
- Simplify on changed LTGs.

- The capability of logic restructuring.
- Transform the rewired threshold network into Boolean domain and verify the correctness.
- Use verify command with SIS.

[2] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, “Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies,” in Proc. Design Automation Test in Europe Conf., 2004, pp. 904-909.

Table I

Table II

- Rectification
- Critical effect

- Terminologies

- Introduction
- Rewiring
- Rewiring flow
- Preliminary
- Preprocess
- Input grouping and gate decomposition

- Target wire removal
- Useless threshold gate
- Useless threshold group
- Critical input
- Useless input

- A rewiring technique for threshold networks is proposed.
- It efficiently provides the capability of logic restructuring.

- A simplification procedure for canonicity is also proposed.

- The proposed algorithm will be used in the application of formal equivalence checking in the near future.