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Convolution codes （ 卷积码）

Chapter 8. Convolution codes （ 卷积码）. 李莉 . 信息机电学院 . SHNU. Linear codes: 1 infor. bit  1 codeword; (n,k)or [n,k,d] ， k-bit infor.  one n-bit codeword Convolution code: . 1 infor. bit  m codewords ; (n,k,m) k-bit infor.+ m previous infor.bits  1 n-bit codeword

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Convolution codes （ 卷积码）

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  1. Chapter 8 Convolution codes （卷积码） 李莉.信息机电学院. SHNU

  2. Linearcodes: 1 infor. bit 1 codeword; (n,k)or [n,k,d]，k-bit infor.  one n-bit codeword Convolution code:. 1 infor. bit m codewords; (n,k,m) k-bit infor.+m previous infor.bits 1 n-bit codeword Representation to convolution code: Algebraically, discrete convolution, generator matrices, polynomials; 解析法：离散卷积法、生成矩阵法、码多项式法； Graphically, tree, trellis, state diagrams. 图形法：树图法、格图法、状态图法. SHNU.信息机电学院

  3. g0 g1 g2 g3 u g4 v 8.1 Convolution (卷积) The discrete convolution. 1)Linear feed-forward shift register the links: g0, g1, g2, g3, g4 = 0, the link is absent or 1, the link is present. Input sequence: u=( u0 u1, u2,u3,…) (输入码序列). output sequence: v=( v0 v1, v2,v3,…) (输出码序列). Assuming the initial states of the shift registers =0, output: 1sttick: v0=u0g0. 2ndtick: v1=u1g0+u0g1. 3rd, v2=u2g0+u1g1+u0g2. 4th , v3=u3g0+u2g1+u1g2+u0g3. (8.1) 5th , v4=u4g0+u3g1+u2g2+u1g3+u0g4. 6th , v5=u5g0+u4g1+u3g2+u2g3+u1g4.  A register with m stages each input ~ m+1 outputs. SHNU.信息机电学院

  4. 2) Outputs for a finite input sequence The last input should appear at the output, an addition m zero inputs are required. The input: u=(u0 u1 u2 … u7,0000), the last outputs: v7= u7g0+u6g1+u5g2+u4g3+u3g4. m=4 v8= u8g0+u7g1+u6g2+u5g3+u4g4. v9= u9g0+u8g1+u7g2+u6g3+u5g4. v10= u10g0+u9g1+u8g2+u7g3+u6g4. v11= u11g0+u10g1+u9g2+u8g3+u7g4. Setting u8=u9=u10=u11=0, All the 7 inputs appear at the output, the output sequence is completed. Any further zero inputs  a zero output. The additional m 0 bitsreturns reg. to zero state. The m 0 should not be confused with the information bits. v8=u7g1+u6g2+u5g3+u4g4. v9= u7g2+u6g3+u5g4. v10= u7g3+u6g4. v11= u7g4. SHNU.信息机电学院

  5. 3) Discrete convolution For a LFFSR with m stages and links gi, i=0,1,2,…,m feeding into a modulo-2 adder, the output from the adder is : vj= uj-rgr.= u*g (8.2, 8.3) where uj-r=0, if j<r. operation* denotes convolution. Each output vjis a convolution of(m+1) input with g0, g1,…,gm. Generator sequence g=(g0, g1,…,gm),生成序列 Discrete convolution Physical vision (物理含义): 10 A window of (m+1) bits are multiplied by g0, g1,…,gm and added together. 20 The window is then slid along the input sequence by 1 bit and multiplication and summation repeated. 30 The process continues until the window has covered the entire input sequence. SHNU.信息机电学院

  6. g0 g2 u g3 v2 v1 4) Determination of generator sequence 10 by inspection of the shift register circuit or 20 by considering the impulse response when the input u=(1 000…0), 1 followed by m 0s. The impulse response gives the generator sequence g. N.B. The generator sequence is not the output of the shift register, But the output from the modulo-2 adder. I.e A line of stages feeding into more than one modulo-2 adder will have a generator sequence for each adder (同一列移存器送入二个以上的模2 加法器，则每个加法器输出有自己的生成序列). by inspection：v1 and v2g sequences g1=(g0 g1 g2 g3)=(0011) g2=(g0 g1 g2 g3)=(1011) SHNU.信息机电学院

  7. v(1) u(1) v(2) v u(2) v(3) v(4) u(k) v(n-1) u v(n) 8.2 Encoding convolution codes  (n,k,m) Convolution Code (CC). 1) Structure 10k LFSRs, num. of stages may different. (in Space)ithLFSR’s input sequence: u(i)=(u0(i)u1(i)u2(i) …) , i=1,2,…,k. (8.4) (in Time)Bth tick, k-bit input block uB=(uB(1)uB(2) …uB(k)) , B=0,1,2,…,L,.... The whole u=(u0(1)u0(2) …u0(k), u1(1)u1(2) …u1(k), u2(1) u2(2) …u2(k) ,…) (8.5) 20Memory order (存储器级数，编码存储): The max. num. of stages m in any shift register. (k-bitsinput 在编码器中需存储的单位时间数。) Fig.8.4 Encoder for an (n,k,m) convolution code SHNU.信息机电学院

  8. 1 in-bit affects the n out-bits, 1 in-bit stays in the encoder for up to m+1 inputs, 1 input bit affects n(m+1) output bits. 30Output:  n modulo-2 adders whose inputs depends on the particular code. jthadders output sequence: v(j)=(v0(j)v1(j)v2(j) …) , j=1,2,…,n. (8.5) Bth tick, n-bit output block vB=(vB(1) vB(2) …vB(n)) , B=0,1,2,…,L+m,…. the whole v=(v0(1)v0(2) …v0(n), v1(1)v1(2)…v1(n), v2(1)v2(2)…v2(n) , …) (8.7) 40Constraint length (编码约束长度): NAn(m+1) (相互约束的码元个数) **Constraint (约束度): N=m+1. (相互约束的码段个数). m:the parameter of the complexity of an encoder. SHNU.信息机电学院

  9. The n-bitvL block leaving the encoder depends on the k-bit entering the encoder up to m previous k-bit input blocks. 2) Finite Input and output : If u(i) is a finite sequence u(i)=(u0(i)u1(i)u2(i) … uL-1(i) ) , i=1,2,…,k. L=length(u(i)) uB=(uB(1)uB(2) …uB(k)) , B=0,1,2,…,L-1. u is a total of kL bitsinput.  An output sequence v(j) of length L+m, v(j)=(v0(j)v1(j)v2(j) … vL+m-1(j) ) , j=1,2,…,n. vB=(vB(1) vB(2) …vB(n)) , B=0,1,2,3…,L+m-1 v=(v0(1)v0(2) …v0(n), v1(1)v1(2)…v1(n), v2(1)v2(2)…v2(n) , … v(1)Lv(2)L…v(n)L, …, v(1)L+m-1v(2)L+m-1…v(n)L+m-1) (a total of n(L+m) bits output) the last m blocks of vthe additional m zero inputs required to return the encoder to its zero state. SHNU.信息机电学院

  10. v(1) v u(1) v(2) u(2) v(3) u(3) u v(4) An (4,3,2) CC Encoder 3) The generator sequences : A LFSR n modulo-2 adders n generator sequences. & the (n,k,m) CC has k LFSRnk generator sequences. Eg8.1a An encoder for the (4,3,2) CC. Input k=3, outputs n=4 , memory order m=2. A total of 4*3=12 g sequences to determine the output. Let g(i,j)=(g0(i,j) g1(i,j) g2(i,j) …gm(i,j)) the g sequence connecting the ithinput to the jth output. g(1,1)=(g0(1,1)g1(1,1)g2(1,1))=(100); g(1,2)=(100); g(1,3)=(100); g(1,4)=(100); g(2,1)=(g0(2,1)g1(2,1)g2(2,1))=(000); g(2,2)=(110); g(2,3)=(010); g(2,4)=(100); g(3,1)=(g0(3,1)g1(3,1) g2(3,1))=(000);g(3,2)=(010); g(3,3)=(101); g(3,4)=(101); (8.8) SHNU.信息机电学院

  11. Example 8.1b Determine the output sequence from the (4,3,2) CC encoder shown in Eg.8.1a, given the input sequences u=(110,011,101) Solution: The input blocks is L=3 , each in-block length =3-bit. The register order m=2. The output blocks are (L+m)=5, each output block=4-bit. The total number of output bits are (L+m)n=(3+2)*4=20bits. ur=0, if r<0. First the inputs should be transformed from sequence to parallel blocks of 3 bits (输入序列要进行串并转换，一组组地同时送入3个LFSR). SHNU.信息机电学院

  12. ∵v(i,j)=u(i)*g(i,j), & the 3 LFSR’s input sequences u(1)=(u0(1) u1(1) u2(1)00) =(10100), u(2)= (11000), u(3)= (01100) Then the output sequence to each adder, Ticks: r = 0, 1, 2, 3, 4, 5 … 1st adder: vr(1)=ur(1)= 1,0, 1, 0, 0, 0,… 2nd adder : vr(2)=ur(1)+ur(2)+ur-1(2)+ur-1(3)= 0, 0, 1, 1, 0, 0,… 3rd adder : vr(3)=ur(1)+ur-1(2)+ur(3)+ur-2(3)= 1, 0, 1, 1, 1, 0,… 4th adder : vr(4)=ur(1)+ur(2) +ur(3)+ur-2(3) = 0, 0, 0, 1, 1, 0,… Finally transform from the 4 bits parallel block into the final output sequence v=(1010 0000 1110 0111 0011 0000…) SHNU.信息机电学院

  13. 4) Error-control properties (各种距离度量) The error-control properties of CC  the distance characteristics of the resulting encoded sequences. However with CCs there are several minimum distance measures. The most important distance measure is Minimum free distance: it is defined as the minimum distance between any two encoded sequences. As CCs are linear codes v1, v2 v3 =v1+v2, WH(v3)=d(v1,v2) . & v30 if v1v2.  the free distance of a CC = the minimum-weight sequence of any length produced by a nonzero input sequence. The definition of free distance includes all sequences and not just sequence with the same length. SHNU.信息机电学院

  14. G0 G1 G2 … Gm 0 0 … 0 G0 G1 G2 … Gm 0 … 0 0 G0 G1 G2 … Gm … . … (8.15) G= gr(1,1) gr(1,2) … gr(1,n) gr(2,1) gr(2,2) … gr(2,n) ┇ ┇ gr(k,1) gr(k,2) … gr(k,n) Gr= (8.16) 8.3 Generator matrices for convolutional codes (卷积码的生成矩阵) If we define a matrix G, its elements are the g sequence, Given an input sequence u, the output sequence v can be obtained by matrix multiplication: v =uG (8.14) SHNU.信息机电学院

  15. 8.4 Generator polynomials for convolution codes 1) Definition of input, output, and generator polynomials of CC ** The input sequence u=(u0u1u2…) ,  the input poly. u(D) u(D)=u0+u1D+u2D2+… (8.18) D is the unit-delay operator , a delay of 1 bit. E.g. u1 is 1 bit delay relative to u0. Bit u2 is 2-bit delay relative to u0, 1-bit delay relative to u1. ** An output sequence v=(v0v1v2…) ,  output poly. v(D) v(D)=v0+v1D+v2D2+… (8.19) ** If v(D) is the output arising from u(D) then v(D)=u(D)g(D) (8.20) the generator polynomial. SHNU.信息机电学院

  16. 2) Determination of g(D) The g(D) from the encoder. ** Each link to a modulo-2 adder contributes a Dr term to g(D) r is the number of stages that a bit has to pass through to arrive at the adder. ** The rth component of the generator sequence g=(g0, g1,…,gm) gr= 0 , exist a linkto the adder, after the rth stage 1 , no linkto the adder, after the rth stage rth component in the g(D) is grDr. ** For m stages, the generator polynomial g(D)=g0+g1D+g2D2+…+gmDm (8.21) SHNU.信息机电学院

  17. 3) The generator polynomials for an arbitrary (n,k,m) CC ** An (n,k,m) CC has k generator polynomials for each of the n output sequences, a total of nk generator polynomials. g(i,j)(D) gr(i,j)Dr (8.22) g(i,j)(D): for the jth output arising from the ith input, gr(i,j): the components of the generator sequence g(i,j). ** The jth output polynomial for (n,k,m) CC is v(j)(D)= u(i)(D)g(i,j)(D) (8.23) j=1,2,…,n. The total output v(D): v(D)= Dj-1v(j)(Dn) (8.24) The components of v  given by the coefficients of v(D). SHNU.信息机电学院

  18. 8.5 Graphical representation of convolution codes (卷积码的图形表示, 树图,格图，状态图) CCs can be represented graphically using tree, trellis and state diagrams (树图，格图，状态图),  show the state of a register and the encoder output for all possible inputs. The state of a register: the contents of the stages at a given point during encoding. The trellis diagram plays an important role when decoding using the Viterbi algorithm Take (2,1,2) as an example to illustrate the graphical representations. SHNU.信息机电学院

  19. v v(1) Qj Qj-1 Qj-2 v(2) u A (2,1,2) convolution encoder Example 8.2 An encoder for (2,1,2) CC. Structure.  at input point j, the encoder can be in one of the 4 states Qj-1Qj-2=Si=00,01,10,11, i=0,1,2,3.  The output: as sequence vj(1)vj(2). vj(1) = Qj+Qj-1+Qj-2 vj(2) = Qj +Qj-2 j=0,1,2,3,… Specifications: The encoder has memory M=2. The code's rate is k/n=1/2. The encoder has three flip-flops;  the code has constraint 3 SHNU.信息机电学院

  20. 10 11 01 01 10 10 01 00 11 11 0 input 1 input 00 00 1) (2,1,2) CC. State diagrams (状态图): Branches: transitions from one state Si to another Sj. The output: next to the relevant branch. Given an arbitrary input u=(u0u1u2…) The output,next statefollowing the transitions via the state diagram, v=(v0(1)v0(2)v1(1)v1(2)…) is nonsystematic CC. a)  the input sequence u=(1101 00). Find the output of the (2,1,2) CC encoder. States Qj-1Qj-2 S0=00 S1=01 S2=10 S3=11 Out vj(1)vj(2) State diagram for the (2,1,2) CC. 2bits: return to zero state SHNU.信息机电学院

  21. 10 11 01 01 10 Ticks j Input bit Qj Qj-1Qj-2 output vj(1)vj(2) Transition to Qj-1Qj-2 10 01 00 0 00 00 S0 11 11 0 input 1 input 00 11 1 1 00 10=S2 01 2 1 10 11=S3 01 3 0 11 01=S1 00 00 4 1 01 10=S2 10 5 0 10 01=S1 11 6 0 01 00=S0 For (2,1,2) CC, & input u: The register order m=2. L=4 , The output blocks are (L+m)=6, length(output block)=2-bit. The total number of output bits: (L+m)n=6*2=12bits. starting from S0=00, return to zero state The final output: v=(11,01,01,00,10,11). SHNU.信息机电学院

  22. 2) Tree diagrams (树图) for the (2,1,2) CC. output 10 S3 10 States Qj-1Qj-2 S0=00 S1=01 S2=10 S3=11 Out vj(1)vj(2) S3 01 01 S1 S3 00 S2 01 S1 11 11 S0 S2 01 S3 00 S2 10 10 S1 S1 11 S2 11 S0 00 Start S0 S0 10 S3 01 S3 01 11 S1 S2 00 1 input 0 input S2 10 S1 11 00 S0 S0 01 S3 11 S2 10 S1 00 S0 11 input sequence u=(1101 00) output: v=(11,01,01,00,10,11). S2 00 S0 00 S0 Time SHNU.信息机电学院

  23. 3) Trellis diagrams (格图) for the (2,1,2) C: Output Current State States Qj-1Qj-2 S0=00 S1=01 S2=10 S3=11 Out vj(1)vj(2) Next State 10 10 10 10 S3 01 01 01 01 01 01 01 01 S2 10 10 10 00 10 00 00 S1 11 11 11 11 11 11 11 11 11 0 input 1 input 11 S0 00 00 00 00 00 00 00 00 Start Time j = 1 2 3 4 5 6 7 input sequence u=(1101 00) output: v=(11,01,01,00,10,11). 6 ticks needed Time SHNU.信息机电学院

  24. 8.6 The Viterbi decoder 1) The Viterbi decoder is a ML decoder. find the path that is the least distance away from the decoder input w. The distance metrics. 2) Branch metric (分支度量): For a BSC, the branch metric is the Hamming distance between the branch output and the corresponding decoder input (译码器输入w的子码。). 3) Path metric (部分路径度量) Each path metric = (branch metrics forming the path). Survivor branch and path (留存支路和部分路径): The branch and the path with lower metric. If the path metrics are the same then either path can be taken as the survivor. Note that metric values depend on the decoder input and are not fixed attributes of a trellis. SHNU.信息机电学院

  25. t a b c d 1 - a 0 - 1 - b 0 - c - 0 - 1 01 d S3 10 - 0 - 1 00 S2 11 S1 00 S0 4) Viterbi's decoding algorithm for (2,1,2) CC S= {a,b,c,d: S0,S1,S2,S3}. If s, t S , B(s,t) = 0 transition by a 0 input. 1 transition by a 1 input. not defined. No links lj-1,j(s,t) = the Hamming distance between the encoder 2-bit output and the received 2-bit subcode, on the trellis edge joining sj-1 to tj. l j-1,j(s,t)= + . no such edge Viterbi's algorithm computes2 metrics: The metrics j(s), sS,: the length of the shortest path from a0 to sj; the survivor Bj(s) is a binary string of length j which represents a shortest path from a0 to sj. s SHNU.信息机电学院

  26. 10. Initially set 0(a) 0, and 0(a)=+  for all sa. Set B0(a)= (空), j=1. 20. For each sS, find a tS for which j-1(t)+lj-1,j(s,t) is a minimum. Then set j(s) j-1(t)+ lj-1,j(s,t), Bj(s)  Bj-1(t)*B(s,t). The operation * : concatenation(串联), e.g. 1101*0=11010 30. If j=L+m, output the first L bits of Bj(a) and stop; otherwise set j j+1, go to step 2. L: the information length, m: the degree of the encoder. SHNU.信息机电学院

  27. Key points to chapter 8: 1. Concept of (n,k,m) convolution code, 2. (n,k,m) CC Encoder input k-bit infor block. output n-bit codeword block. Each LFSR input: length L The LFSR Total Output : (L+m)*n bits 3. Representations to conv. code G g(D) Graphical: tree, trellis, state diagram 4. Viterbi decoder Understand. SHNU.信息机电学院

  28. Homework: 1.http://xxjd.shnu.edu.cn/下载中心/more... /problems.pdf P255, 8.1 8.2 8.5 8.6 SHNU.信息机电学院

  29. END & THANK YOU！ SHNU.信息机电学院

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