Introduction to Parallel Processing. CS147 Tung Sze Ming. Topics Covered. An Overview of Parallel Processing Parallelism in Uniprocessor Systems Parallelism in Multiprocessor Systems Flynn ’ s Classification System Topologies. An Overview of Parallel Processing.
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Each stage of a reconfigurable arithmetic pipeline has a multiplexer at its input. The multiplexer may pass input data, or the data output from other stages, to the stage inputs. The control unit of the CPU sets the select signals of the multiplexer to control the flow of data, thus configuring the pipeline.
To
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registers
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1
MUX
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3
S1 S0
*
LATCH
0
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MUX
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S1 S0

LATCH
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MUX
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3
S1 S0
+
LATCH
0
1
MUX
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S1 S0
Data Inputs
0 0
x x
0 1
1 1
Although arithmetic pipelines can perform many iterations of the same operation in parallel, they cannot perform different operations simultaneously. To perform different arithmetic operations in parallel, a CPU must include a vectored arithmetic unit.
A vector arithmetic unit contains multiple functional units that perform addition, subtraction, and other functions. The control unit routes input values to the different functional units to allow the CPU to execute multiple instructions simultaneously.
Data
Input
Connections
Data
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Data
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%
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DEF
Topology of a multiprocessor system refers to the pattern of connections between its processors. Various factors, typically involving a costperformance tradeoff, determine which topology a computer designer will select for a multiprocessor system.