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RGMII. MAC RX/TX Synchronous CAPTURE WITH 16802A AGILENT LOGIC ANALYZER Pascal GRISON Application Engineer. Objectives. Define a Logic Analyzer Configuration that would enable Synchronous capture of RGMII MAC interface Ideally Capture simultaneously TX and RX.

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Pascal GRISON Application Engineer



  • Define a Logic Analyzer Configuration thatwouldenableSynchronous capture of RGMII MAC interface

  • Ideally Capture simultaneously TX and RX

Rgmii mac interface details

RGMII MAC Interface details


Full Duplex

125MHz Clock (for GbE)

TX Side

TXC (Dual EdgeClocking)

TD[4] TD0 TD1 TD2 TD3

D3..DO sent on Rising TXC

D7..D4 sent on falling TXC


TX_EN sent on Rising TXC

TX_ERR sent on falling TXC

RX Side

RXC (Dual EdgeClocking)

RD[4] RD0 RD1 RD2 RD3

D3..DO sent on Rising RXC

D7..D4 sent on falling RXC


RXDV sent on Rising RXC

RXERR sent on falling RXC

Capture tx transactions

Capture TX Transactions

NeedSynchronousSampling: State Mode

Need Double EdgeClocking:

->State Samplingat 250MHz on 125MHz Clock

-> Logic Analyzer

-> Demux Mode to rebuild Data[8]

Rgmii tx timings

RGMII TX Timings

TXD[3:0] & TXEN willbeClocked on Risingedge of TXC

TXD[7:4] & TXERR willbeClocked on Fallingedge of TXC

-> Weneed to use BothEdgesClocking (DEMUX Mode)

Demux sampling mode

DemuxSampling Mode?

In the Demultiplex state sampling clock mode, you can demultiplex data being probed by one pod into the logic analyzer memory that is normally used for two pods. Demultiplex mode uses the master and slave clocks to demultiplex the data.

When the slave clock occurs, data captured on the pod is saved into the slave latch for the other pod in the pod pair. Then, when the master clock occurs, data captured on the pod, as well as the slave latch data, are saved in logic analyzer memory. As with master/slave mode, if multiple slave clocks occur before the next master clock, only the most recently acquired slave data is saved into logic analyzer memory.

2) -> TXCK FallingEdge

1) -> TXCK RisingEdge

Configure demux sampling

Configure DEMUX Sampling

Config Logic Analyzer as DEMUX STATE on TX CLOCK

RisingEdgeis Salve Clock and Happend First

FallingEdgeis Master Clock and Happend Second

Master Clock Event activate Storage of one State Sample

Up to 16M available (with Option 32)

Configure bus setup

Configure Bus SETUP

Config of Logic Analyzer buses


TXDATA as 8 bit bus

TXDATA[3:0] & TXEN willbeClocked on Risingedge of TXC

TXDATA[7:4] & TXERR willbeClocked on Fallingedge of TXC

FULL DATA[7:0] + TXEN +TXERR willbestored in one memoryspace in logic Analyzer everyclock Cycle

Up to 16M TX Packet Can beAcquired (with option 32M)

Overview of logic analyzer for tx demux

Overview of Logic Analyzer for TX DEMUX

Current Config is the following:

One Analyzer configured as one State Acquisition system to Demux and Acquire TX Packets

What about rx

What About RX?

WeNeed to Acquire TX & RX Packets

RX Clockbehave in similar dual edge as TX Clock

Rgmii rx timings

RGMII RX Timings

RXC isderivedfromreceived Ethernet Packets (Asynchronousfrom TXC)

RXD[3:0] & RXDV willbeClocked on Risingedge of TXC

RXD[7:4] & RXERR willbeClocked on Fallingedge of TXC

-> Weneed to use BothEdgesClocking (DEMUX Mode)

How to capture rx packets

How to Capture RX Packets

RX ClockisAsynchronous to TX Clock

RXDATA and RX_CTL are muxed

TX Clock CANNOT beused to Acquired RX Data

Need to definetwoindependant State Demux Acquisition System, one based on TXClock one on RXClock…

Can we do this on a Single Logic Analyzer?

Now let s split your 68ch logic analyzer into two 34ch logic analyzers

NowLet’s Split Your 68Ch Logic AnalyzerintoTwo 34Ch LogicAnalyzers

Agilent LogicAnalyzers has unique capability to split themselves in Two!

We now dispose of two independant logic analyzers in one

Wenow dispose of TwoIndependantLogicAnalyzers in one

Independant Channel Setup

IndependantSalmpling Mode


Independant Triggers

Independant Listing/Waveforms

But Also Capable of

Master/Slave Triggering

Correlated Mesure thanks to


Common Listing/WaveformsCapability

Complete tx rx demux synchonous sampling system overview

Complete TX/RX DemuxSynchonoussampling System Overview

TX Demux Master Trigger

RX DemuxTriggedfrom TX Trigger

Common TX/RX Listing

Common TX/RX Waveforms

Simultaneous 4GSa/s Timing oversampling (TimingZoom) available (capture 16µs around trigger)

Exemple of rgmii tx rx listing

Exemple of RGMII TX/RX Listing

Demo Offline Data / Not real RGMII Capture

Scope logic analyzer time correlated measurements

Scope –Logic AnalyzerTime CorrelatedMeasurements

Use Logicanalyzer to trigger on RGMII Sequence of TX or RX Packets to Trigger Oscillosocpe

Use Glitch or serial Trigger on Oscillosocpe to Trigger Logicanalyzer and findmatching RGMII Packet

Get ALL Analog + Digital signalsDisplayed on single display

Save ALL Analog + Digital signalsDisplayed on single file for post processing or Off-Lineanalysis

Compatible with All current Agilent Scope and LogicAnalyzers

Easy to Setup

Lan based for data transfert & control

2 BNC Cablesfrom Triggers withautodeskewcapability

AutomaticFastwaveform transfert from Scope to Logic Analyzer

Markers correlatedbetween instruments

Exemple of measure on dac digital inputs correlated with analog output

Exemple of Measure on DACDigital inputs correlatedwithAnalog Output

Questions answers

Questions & Answers?

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