A DFT Approach for Diagnosis and
This presentation is the property of its rightful owner.
Sponsored Links
1 / 22

Outline PowerPoint PPT Presentation


  • 51 Views
  • Uploaded on
  • Presentation posted in: General

A DFT Approach for Diagnosis and Process Variation-Aware Structural Test of Thermometer Coded Current Steering DAC's.

Download Presentation

Outline

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Outline 5680390

A DFT Approach for Diagnosis and Process Variation-Aware Structural Test of Thermometer Coded Current Steering DAC's

Rasit Onur Topaloglu and Alex Orailoglu{ rtopalog | alex [email protected] of California, San DiegoComputer Science and Engineering Department 9500 Gilman Dr., La Jolla, CA, 92093


Outline

Outline

  • Current Steering Digital to Analog Converters 101

  • A Process Variation-Aware Soft Fault Model

  • Process Variation Estimation

  • Reduction of Diagnosis Time Using Design for Testability Hardware

  • Experimental Results


Introduction

Introduction

  • Higher precision applications drive Digital to Analog Converter (DAC) resolutions to higher bits day by day

  • Higher bit resolutions increase circuit complexity, hence increase test time and difficulty

  • In thermometer coded circuits, controllability is limited as each bit increment sums current of a new source with previous ones

  • Diagnosis of a fault or test is usually handled by exhaustively trying all input codes


Binary coded current steering principle

Binary-Coded Current Steering Principle

  • Input digital code selects current sources to be added to analog output

  • Iout is the analog output

  • Current sources are in fact implemented by current mirrors using a common on-chip reference current

4I

2I

I

(110) input shown for an 8-bit binary CSDAC (Current Steering DAC)

Iout


Individual current distributions

Individual Current Distributions

  • Soft faults for exponentially valued current sources would contribute integral and differential non-linearity (INL and DNL) degradation during certain transitions e.g. transition from 2^n-1 to 2^n

W1/L1

W2/L2

W1/L1

W2/L2

4I

Iref

I

Iref

4I

I


Impact of binary coding on inl and dnl

Impact of Binary Coding on INL and DNL

Analog

  • Transitions from 2^n-1 to 2^n activate totally differents sets of current sources

  • Due to limited spatial correlation between these groups, DNL will tend to get larger, which implicitly tend to enlarge INL

  • In thermometer-coded (TC-CSDACs), in these transitions, one more current source is added only, and hence outputs of these two codes highly correlated due to the 2^n-1 common elements

INL: max difference between overall real and ideal lines

DNL: max of stepwise differences

Digital

7

8


Thermometer coded csdacs tc csdacs

Thermometer-Coded CSDACs (TC-CSDACs)

  • (110) in binary is (0111111) in thermometer code

  • Equal weighting of current sources prevents significant impact for faulty sources

  • Error correction capability is another attractive reason for choosing thermometer code ex:0111011 not possible as 1’s should be consecutive

I

I

I

I

I

I

I

I

(0111111) input for an 8-bit thermometer coded CSDAC

Iout


Diagnosis restriction of tc csdacs

Diagnosis Restriction of TC-CSDACs

  • Current sources indexed with fixed bit positions

  • Fixed indexes imply a controllability restriction

  • Diagnosis time for a faulty current source exponentially increases as compared to binary coded CSDACS

I

I

I

I

I

I

I

I

(0111111) input for an 8-bit thermometer coded CSDAC

Iout


Design considerations for tc csdacs

1

12

15

3

13

5

7

10

9

8

6

14

4

16

11

2

Design Considerations for TC-CSDACs

  • Current sources laid out in common-centroid layout style to minimize impact of process variations

  • A number of most significant bits (MSB’s) and least significant bits (LSB’s) are grouped within themselves to further reduce process variation impacts

ex: In a 16-bit converter, current sources indexed by consecutive number laid out on separate corners


A practical tc csdac architecture

m MSB’s are interpolated by n LSB’s where B, total number of bits, is m+n

Input to the TC-CSDAC is binary, hence binary to thermometer decoders used in the circuit

Proposed fault model can be applied to MSB and LSB parts separately

A Practical TC-CSDAC Architecture


Process aware structural soft fault model

Process-Aware Structural Soft Fault Model

  • Process variations should not be mistaken as faults

  • The proposed fault model: one current source might have an additional deviation from process variation effected value due to any modeled or un-modeled fault

probability

For each die, a current source will have a fixed value picked up from its probability density function, caused by process variations

Isource

I


Estimation of process variations

Estimation of Process Variations

  • Current sources are systematically correlated due to their close locations on die

  • Current sources can be represented as a sum of independent components through a technique called Principal Component Analysis (PCA)

  • Principal components corresponding to largest eigenvalues account for most of the variation

  • Ratio of selected eigenvalues to all eigenvalues can be used to ensure a minimum variation

I : normalized current source variables

U : eigenvectors of correlation matrix

C : principal components


Estimation of process variations1

Estimation of Process Variations

  • A reduced number of principal components, M<N, is equivalent to deleting some of the columns

  • Then, M of these equations can be chosen to obtain an M equation-M unknown system

  • The choice is made for consecutively indexed sources, as each source individually requires two measurements due to controllability restriction


Process variation aware test nominals

Process Variation-Aware Test Nominals

  • M sources are measured for each chip, U is calculated from correlation matrix, hence only C values are left to be determined

  • Once C values are calculated, unmeasured N-M source I values can be calculated

  • Hence, these steps provide process-variation aware nominal values for each current source using few measurements, as N>>M even for 98% variation


Acquiring principal components on chip

Acquiring Principal Components On-Chip

  • Analog current is measured for up to principal component number of times; as low as ~ 6 measurements satisfactory to account for 98% variation

  • No additional hardware is required to take these measurements, for ex. 6 consequent input codes, (0..0000000),(0..0000001),(0..0000011),.., (0..0111111), can be used to get these measurements


Correlation model

Correlation Model

  • Output of a current source is spatially correlated to neighboring sources on layout as a result of silicon manufacturing steps

  • A spatial distance2 correlation model is used

  • According to the correlation model, the correlation starts from a number close to 1 and decreases towards 0 with distance between each pair of sources


Design for test dft hardware

Design for Test (DFT) Hardware

  • One more decoder and some combinational gates added to the original decoder

  • Similar modification done for row selection hardware

  • test_sel=0 : original mode

  • test_sel=1 : one column is selected using Ci inputs and setting row_sel=1


Reduction of diagnosis time using dft

1

12

15

3

13

5

7

10

9

8

6

14

4

16

11

2

Reduction of Diagnosis Time using DFT

  • Instead of exhaustively measuring current sources, particular groups of them are summed & measured

  • This reduces the diagnosis time from quadratic to linear

  • Process-variation aware nominal test points are used for each source to create variation aware nominals

  • One row selected such that the sum of current sources within are deviating from the average of remaining row sums; similarly for columns


Outline 5680390

Experimental Results

  • Even a minor 20% deviational soft fault around process variation estimated values can be caught with ~100% efficiency!


Error rates for process estimation

Error Rates for Process Estimation

  • Examination of normalized error in last column reveals that difference between real and estimated values are almost negligible using 6 principal components


Outline 5680390

Robustness for Increased Requirements

  • Increasing bit requirements indicate detection of lower deviational faults due to averaging of non-faulty sources approaching the population mean


Outline 5680390

Conclusions

  • A process variation aware DFT method is proposed

  • Even minor soft faults can be caught with the proposed technique due to accounting of process variations

  • A fast diagnosis procedure is proposed with reasonable addition of DFT HW

  • The proposed technique becomes more robust for increased bit requirements


  • Login