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Quarterly Technical Report 1 for Pittsburgh Digital Greenhouse

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Quarterly Technical Report 1 for Pittsburgh Digital Greenhouse. High Speed CMOS A/D Converter Circuit for Radio Frequency Signal. Kyusun Choi. Computer Science and Engineering Department. The Pennsylvania State University. Project goals for this quater.

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slide1

Quarterly Technical Report 1

for

Pittsburgh Digital Greenhouse

High Speed CMOS A/D Converter Circuit

for Radio Frequency Signal

Kyusun Choi

Computer Science and Engineering Department

The Pennsylvania State University

slide2

Project goals for this quater

  • Design a 6 and 8 bit TIQ based flash ADC circuits and CMOS layouts
  • Design the first prototype chip:
  • 6 and 8 bit flash ADC
  • 3. Chip fabrication submission
slide3

Accomplished project milestones for this quarter

  • Designed 6, 8, and 9 bit TIQ based ADC circuits and CMOS layouts in 0.25 m
  • Designed the first prototype chip:
  • 6, 8, and 9 bit flash ADC
  • Fabrication submission preparation
  • Chip fabrication submission:
  • - Submission date: 4/2/2001
  • - Vendor: MOSIS with TSMC 0.25 m foundry
  • - Expected prototype chip delivery date: 7/16/2001
slide4

Design Method

  • Systematic Variation Approach
  • - Systematic Parameter Variation (SPV)
  • 2. CAD Tools
    • - MAX for layout
    • - SUE for schematic capture
    • - HSPICE for circuit simulation
    • - Custom designed a set of C programs
  • 3. Experiment base, Spice Model Base
slide5

Chip Layout Design (1)

Chip Block Diagram

slide6

Chip Layout Design (2)

  • Dimension
  • ADCs
  • Chip size (2580um * 2580um)
slide7

Chip Layout Design (3)

Layout

- 6bit (0.24 um)

slide8

Chip Layout Design (4)

Layout

- 6bit (1.00 um)

slide9

Chip Layout Design (5)

Layout

- 8bit (0.24 um)

slide10

Chip Layout Design (6)

Layout

- 8bit (0.50 um)

slide11

Chip Layout Design (7)

Layout

- 9bit (0.50 um)

slide12

Chip Layout Design (8)

Layout

- 9bit (1.00 um)

slide15

Simulation Results (1)

- pad delay : 0.864 ns

slide16

Simulation Results (2)

- 6bit (0.24um)

slide17

Simulation Results (3)

- 6bit (1.00um)

slide18

Simulation Results (4)

- 8bit (0.24um)

slide19

Simulation Results (5)

- 8bit (0.50um)

slide20

Simulation Results (6)

- 9bit (0.50um)

slide21

Simulation Results (7)

- 9bit (1.00um)

slide22

Features of the TIQ based ADC

  • High Speed
  • Relatively small area
  • 3. Relatively low-power
slide23

Issues to Be Addressed in Future

1. Dynamic fine-tuning

2. Supply voltage variation compensation

3. Temperature variation compensation

4. Process variation compensation

5. Lower power

6. FIFO design for on-chip high-speed data acquisition

slide24

Innovation Challenges

  • 2 GSPS with 0.18um CMOS
  • Custom layout CAD tool
  • 10bit and 12bit ADC
  • Low power
  • Dynamic calibration
    • Offset
    • Gain
    • Temperature
    • Power supply voltage
    • Process parameter variation
slide25

Summary

  • High speed ADC for RF
  • ADC core - 6, 8 and 9 bit design
    • first prototype chip (silicon test)
    • 0.25 m MOSIS (tsmc) process
    • CMOS digital logic technology
  • Future ready
  • Dynamic calibration
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