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M.Caselle

MOS transistor & introduction to analog layout. KSETA – KIT-Center Elementary Particle and Astroparticle Physics. 06 February 2014. M.Caselle. n-MOS Field Effect Transistor. MOS transistor (3D view). M etal. Gate. Drain. Source. MOS. O xide (dielectric). W eff.

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M.Caselle

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  1. MOS transistor & introduction to analog layout KSETA – KIT-Center Elementary Particle and Astroparticle Physics. 06 February 2014 M.Caselle

  2. n-MOS Field Effect Transistor MOS transistor (3D view) Metal Gate Drain Source MOS Oxide (dielectric) Weff Semiconductor (substrate) n+ n+ Leff n+ regions LDrawn P-substrate Three terminals device (Source, Drain and Gate) Complementary MOS (CMOS) technologies, both n-MOS and p-MOS transistors are available G G MOS transistor (p-type) – front section MOS transistor (n-type) – front section S S D D p+ p+ n+ n+ N-substrate P-substrate KSETA , Karlsruhe 26 February 2013 – M. Caselle

  3. n-MOS Field Effect Transistor (II) MOS transistor (n-type) MOS interface  capacitance vs. substrate Drain and source n+ regions  diode vs. substrate D G Substrate at 0V S NMOS electrical symbol Electrical considerations: Drain and Source will work as two independent diodes with anode connected to bulk If VS < 0V and/or VD <0 G  this suggest that VS and VD must be ≥ 0V S D n+ n+ If VG = 0V no current flow between Source and Drain What about the MOS interface behaviour …. ? P-substrate KSETA , Karlsruhe 26 February 2013 – M. Caselle

  4. MOS interface – (IDS vs. Vgs) Characteristics Hole accumulation + + -+ - - - VG < 0 --- --- --- --- IDS + + + + + + + + D D D + + + + + + + + + + Depletion region ON VG > 0 S S S +++ +++ +++++ +++++ OFF + + + + + + + VTH + + + VGS Negative ions - - - - - - - - - - - - - - - - - - - - Inversion layer VG > VTH > 0 (threshold voltage) G G G S S D S D D n+ n+ n+ n+ n+ n+ + + + + + + + P-substrate P-substrate P-substrate Free electrons + e- e- e- + Drain and Source are connected through with a conductive channel KSETA , Karlsruhe 26 February 2013 – M. Caselle

  5. MOS interface – summarize Accumulation region + + -+ - - - VG < 0 + + + + + + + + + + + + + + + + + + Depletion region VG > 0 + + + + + + + + + + Inversion layer - - - - - - - - - - - - - - - - - - - - G G G S S D S D D VG > VTH > 0 (threshold voltage) n+ n+ n+ n+ n+ n+ + + + + + + P-substrate P-substrate P-substrate Drain and Source are connected through with a conductive channel KSETA , Karlsruhe 26 February 2013 – M. Caselle

  6. n-MOS interface – (IDS vs. VDS) Characteristic + - Inversion layer VG > VTH VD > 0 D D S S IDS VGS3 ------ ------ VGS2 n+ n+ n+ n+ S Free electrons Thickness of the free electrons region depends on VGS VGS3 > VGS2 >VGS1 >VTH P-substrate P-substrate Linear or triode region VGS1 VG > VTH VDS ------ ------ VDS close to zero Channel modulation G VG > VTH D S MOSFET as a controlled linear resistor Ron Typical value few hundred Ohms KSETA , Karlsruhe 26 February 2013 – M. Caselle

  7. n-MOS interface – (IDS vs. VDS) Characteristic + + - - Linear or triode region VGS3 VD > 0 VG > VTH G D VGS2 S S IDS Ids3 High resistance ------ ------ n+ n+ n+ n+ Ids2 Saturation region Channel modulation P-substrate P-substrate VD > 0 VGS1 Saturation region VG > VTH Ids1 VDS > VGS - VTH VDS ----- Large VDS -- VDS1 = VGS1 - VTH Channel pinch-off (point with no free charges inside) Drain Ids = gm * VGS D IDS VG > VTH Rout IDS S Source KSETA , Karlsruhe 26 February 2013 – M. Caselle

  8. IDS vs. VDS working regions VGS > VTH and VDS ~ 0V IDS Analog Circuit D IDS G VDS VGS3 S VGS > VTH VDS > VGS - VTH VGS D VGS2 Linear region High resistance Saturation region MOS works as a switch (ON) (low serial resistance) VGS1 S VGS ~ 0V VDS any values VDS S D MOS works as a switch (OFF) (high resistance of ten/hundred megaohms) Digital Circuit KSETA , Karlsruhe 26 February 2013 – M. Caselle

  9. The CMOS technology Complementary MOS (CMOS) is a technology for constructing integrated circuits CMOS technology is used in microprocessors, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, etc.. CMOS inverter (NOT logic gate) p-mos A input signal Q output signal 0 1 0 1 0 1 0 1 0 1 n-mos Vss could be = 0V In which way it is possible to merge two different transistor typologies on common substrate ? MOS transistor (n-type) MOS transistor (p-type) G G Require a N-substrate S S D D Require P-substrate p+ n+ p+ n+ Few µm n-well P-device is implemented in a N-type well (n-well) P- substrate KSETA , Karlsruhe 26 February 2013 – M. Caselle

  10. n-MOS technology layout and physical implementation (I) Step 1 – n+ drain/source region Layout view 3D view Width n+ region (RX) P- substrate Drain Source Transistor channel Width n+ n+ Step 2 – drain/source metal contact Layout view 3D view Metal 1 P- substrate Drain and Source metal contact (CA) KSETA , Karlsruhe 26 February 2013 – M. Caselle

  11. n-MOS technology layout and physical implementation (II) Step 3 – poly polygon as channel gate Layout view 3D view Poly-silicon (conductive) Gate Source Drain n+ Transistor channel length P- substrate Step 4 – active area Layout view 3D view Gate n-MOS DONE Source Drain n+ n+ WNMOS P- substrate The MOS structure is automatically recognized by the active area rectangle Active area for n-transistor (green) KSETA , Karlsruhe 26 February 2013 – M. Caselle

  12. p-MOS technology layout and physical implementation (III) Step 4 – p-MOS transistor Layout view 3D view Gate Drain Source WPMOS p+ WPMOS p+ Note that the p-MOS width is increased Step 5 – n-well region Active area for p-transistor (brown) 3D view Layout view Gate p-MOS DONE Drain Source p+ p+ n-well n-well KSETA , Karlsruhe 26 February 2013 – M. Caselle

  13. CMOS technology layout and physical implementation (I) Layout view Schematic view p-MOS M1 VDD S G M1 WPMOS D IN OUT D G M2 M2 WNMOS S n-MOS Combine the n-MOS with p-MOS. Note the different sizes KSETA , Karlsruhe 26 February 2013 – M. Caselle

  14. CMOS technology layout and physical implementation (II) Layout view Schematic view By poly connection (red) VDD metal 1 (large to avoid a large ohmic voltage drop) VDD S G M1 D VGS IN OUT D G M2 S GND metal 1 (large to avoid a large ohmic voltage drop) By metal 1 connection (blue) KSETA , Karlsruhe 26 February 2013 – M. Caselle

  15. CMOS technology layout and physical implementation (III) Schematic view Layout view By metal 1 (blue) VDD VDD metal 1 D G By metal M1 S OUT IN 3D View OUT GND D IN G OUT VDD M2 S n+ n+ GND metal 1 p+ p+ n-MOS n-well p-substrate By metal 1 (blue) p-MOS Poly-gate (red) KSETA , Karlsruhe 26 February 2013 – M. Caselle

  16. Introduction to analog building blocks VDD VDD D G VDS R IN M1 S OUT VGS OUT D R G VDS IN M1 S VGS Common drain Common source R R VDD OUT M2 D D IN1 IN2 G M1 S S VGS VGS Differential pair KSETA , Karlsruhe 26 February 2013 – M. Caselle

  17. VOUT Common source (single stage analog amplifier) MOS OFF VDD A VDD VOUT = VDD – gm * VIN * (R) VOUT = - A * VIN R ID A OUT B C KVL: VOUT = VDD –R*ID D MOS in saturation MOS in Linear region G VDS IN M1 S VIN1 VIN VTH VGS VDD VDD VDD A C B R ID R R OUT OUT D OUT M1 G D IN ron D G IN G M1 IN S S S VIN >> VTH MOS in linear ron very low  close a short VIN is low < VTH MOS is switch OFF ID = 0  VOUT = VDD VIN > VTH MOS in saturation ID = gm* VIN KSETA , Karlsruhe 26 February 2013 – M. Caselle

  18. MOS OFF VOUT Single stage amplifier VDD VDD A* VIN MOS in saturation R ID MOS in Linear region OUT 0 D VIN time VTH G VDS VBIAS IN M1 S Analog signal to be amplified VGS time Polarization voltage offset VDD In many CMOS technologies, it is difficult to fabricate resistors with tightly-controlled values or a reasonable physical size. It is desirable to replace the R with a MOS transistor (current mirror) p-MOS current source for high Resistance rM2 M2 Vbias OUT ID D G Gain = -gm1 * (rM1||rM2) M1 IN rM1 S KSETA , Karlsruhe 26 February 2013 – M. Caselle

  19. VOUT Common drain (Source follower) Used as voltage buffer or level shifter VDD VDD RIN  very high D D G G IN IN M1 M1 B S S VGS VGS ROUT  very low OUT OUT MOS in saturation MOS OFF ID A VOUT =~ VIN Output follows the input R R VIN1 VIN VTH A B VDD D G M1 IN S VGS OUT ID R VIN is low < VTH MOS is switch OFF ID = 0  VOUT = 0 VOUT = R * ID (KVL) VOUT = R * gm (VIN-VOUT) KSETA , Karlsruhe 26 February 2013 – M. Caselle

  20. Differential pair, why ? (Case 2) Noise from power supply VDD R OUT Effect of supply noise on a single-ended amplifier Analog signal line D G IN IN IN M2 M1 M1 S VDD Solution …. VOUT2 VOUT1 VOUT = VOUT1 – VOUT2 Differential circuit KSETA , Karlsruhe 26 February 2013 – M. Caselle

  21. Differential pair VOUT VDD VOUT1 VOUT2 VDD R R R R R R R R A B I2 I1 = ID I1 I2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT1 VOUT1 VOUT1 VOUT1 I2 =ID I1 C VIN2 VIN2 VIN2 VIN2 VIN1 VIN1 VIN1 VIN1 VDD – R*ID M2 M1 M2 M2 M2 M1 M1 M1 VIN1 – VIN2 ID ID ID ID If VIN1–VIN2 << 0  M1 is OFF and M2 ON  I1=0 and I2=ID => VOUT1 = VDD & VOUT2 = VDD - R*ID If VIN1–VIN2 >> 0  M1 is ON and M2 OFF  I1=0 and I2=ID => VOUT1 = VDD -R*ID & VOUT2 = VDD Middle VIN1–VIN2 M1 is ON and M2 ON  ID = I1 + I2=> VOUT1 = VDD-R*I1 & VOUT2 = VDD-R*I2 C A B KSETA , Karlsruhe 26 February 2013 – M. Caselle

  22. Differential pair (II) CMOS technology VDD VOUT VDD – R*ID VDD R R VOUT2 VOUT1 VOUT2 VOUT1 I2 I1 A B B A M1 M2 VIN1 – VIN2 time time ID VIN1 – VIN2 A B Output Vout = Vout2 – Vout1 = gm1,2 * (R) * (VIN1-VIN2) Gain KSETA , Karlsruhe 26 February 2013 – M. Caselle

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