1 / 49

Lithography and Design in Partnership: A New Roadmap

Lithography and Design in Partnership: A New Roadmap. Andrew B. Kahng UCSD Depts. of CSE and ECE abk@ucsd.edu http://vlsicad.ucsd.edu/. Outline. Two Cultures, Two Roadmaps Lithography changes the Design roadmap Design changes the Lithography roadmap Toward a shared Litho-Design roadmap.

cbell
Download Presentation

Lithography and Design in Partnership: A New Roadmap

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Lithography and Design in Partnership: A New Roadmap Andrew B. Kahng UCSD Depts. of CSE and ECE abk@ucsd.edu http://vlsicad.ucsd.edu/

  2. Outline • Two Cultures, Two Roadmaps • Lithography changes the Design roadmap • Design changes the Lithography roadmap • Toward a shared Litho-Design roadmap SPIE Advanced Lithography 2008

  3. Two Mindsets • PROCESS • Golden model of Chip • Polygon data • Don’t know how it was obtained • To sell the wafer, meet spec • shapes and currents • Mechanism for checking: • measure silicon • DESIGN • Golden model of Process • SPICE • Don’t know how it was obtained • To sell the chip, meet spec • power and timing • Mechanism for checking: • verify at “corners” • Don’t know how they were obtained SPIE Advanced Lithography 2008

  4. Package Wafer Die Board Wafer-to-Wafer Lot-to-Lot System Two Kinds of “Beyond the Die” DESIGN PROCESS SPIE Advanced Lithography 2008

  5. Two Roadmaps CD Uniformity MEEF dense line MEEF isolated line Linearity CD MTT Data volume Defect size Chip size Leakage power Dynamic power Max frequency MTTF Reuse Circuit families SPIE Advanced Lithography 2008

  6. DESIGN LITHO Chip size Leakage power Dynamic power Max frequency MTTF Reuse Circuit families CD uniformity MEEF dense MEEF isolated Linearity CD MTT Data volume Defect size BSIM Model WL VDD A1 A2 nr nl C2 C1 B1 B2 BL BLb What Is The Connection? • Device • Model • Circuit • Product • Cost SPIE Advanced Lithography 2008

  7. Outline • Two Cultures, Two Roadmaps • Lithography changes the Design roadmap • Design changes the Lithography roadmap • Toward a shared Litho-Design roadmap SPIE Advanced Lithography 2008

  8. 1. Layout Restriction: RDRs • RETs, DRCs, physics  Risk, Margin, Cost • Give designers freedom from choice • Area cost of RDRs = one-time, inevitable ‘reset’ Irregular active geometry Irregular poly geometry Off-grid contact placement Beyond L3GO: All geometry represented as lines and dots SPIE Advanced Lithography 2008

  9. 45nm (IBM, IEDM06) 45nm Requirement: Grid-Based Layout • Not a slam dunk • Logic: contact landing, diffusion, area optimization • SRAM: SNM  multiple diffusion widths • Clouded by imperfect cost and feasibility analyses • Win: scaling, model guardband reduction, TAT model guardband reduction SPIE Advanced Lithography 2008

  10. 0.4 0.3 0.2 34.1% 34.1% 0.1 0.1% 13.6% 13.6% 2.1% 0.0 1 -3 -2 -1 2 3 Design Impact of Model Guardband • Random Defect Yield (Yr) • Strong function of area (A) • Guardband reduction  less design time, less chip area ! • (Timing closure is easier) • Parametric Yield (Ys) • Function of design guardband • Guardband reduction  less yield at wafer sort • Example: normal distribution with BC / WC = -3σ / +3σ • x% guardband reduction • 0% reduction: Ys=0.9973 • 40% reduction: Ys=0.9281 k = 0  Binomial PDF Worst case (α =  ): Poisson SPIE Advanced Lithography 2008

  11. 158 156 154 152 no clustering 150 alpha=0.42 # of good dice per wafer 148 alpha=0.43 alpha=0.44 146 alpha=0.45 144 alpha=0.5 alpha=1 142 alpha=10 140 alpha=1000 138 0 10 20 30 40 50 60 Reduced GB (%) Guardband Impact = Methodology Lever • UCSD 2007: Design methodology can use model guardband as lever to trade off TAT, chip area and power, and sort yield • Complements variability reductions in the manufacturing process • Random defect yield will increase • Parametric yield will decrease • TAT will decrease • (Moore’s Law: 1% per week) • Example: 20% guardband reduction  4% increase in good die /wafer SPIE Advanced Lithography 2008

  12. 2. Double Patterning Lithography (DPL) • ORAMEX (Ordinary Resist And Multiple Exposure), IBM 1998 • Challenges • Equipment: overlay margin • Design: layout decomposition, design rules, new OPC for DPL + Desired pattern Combined exposure First Mask Second Mask SPIE Advanced Lithography 2008

  13. Layout Fracturing Node Splitting for Touching Features Conflict Graph Construction Conflict Cycle Detection ILP based or heuristic Graph Coloring No Conflict Cycle? Yes Node Splitting for Conflict Cycle Removal Layout Splitting and Coloring • Find min-cost color assignment • Non-touching features with 0 < d(i,j) < tdifferent colors • Touching features assigned different colors incur cost cij SPIE Advanced Lithography 2008

  14. + = = + Smart Dividing Point Selection • Split polygons to have maximum overlap • Reduce CD variation from LES, misalignment SPIE Advanced Lithography 2008

  15. o1 = + o2 Layout Decomposition Two Masks with Extended Overlap Design Change (Increase space) Decomposition (1) Decomposition (2) Design Change (Increase space) Design Change (Reduce size) Limits of Layout Decomposition • Require DPL-compliant design SPIE Advanced Lithography 2008

  16. Hierarchical ILP Solver (UCSD 2008) • Layout decomposition • Solves all conflict cycles with largest possible overlap lengths • Scalable runtime from hierarchical graph decomposition • 32nm dense layout: ~2400 sec / mm2, 1 CPU, fully parallelizable • Testcase: 0.5mm x 0.5mm block, TSMC 90nm • 20K standard cells • High layout density: 90% utilization • GDS scaled down by 0.4 minimum width: 40nm  minimum space: 56nm • Vary distance threshold t from 60nm to 88nm • 1.1 to 1.6 times minimum spacing SPIE Advanced Lithography 2008

  17. 3. Analyses of Bimodal CD Distribution • Bimodal distribution in DPL • Poly gates made by two independent processes • Gate CD distributions in two groups can differ • Loss of correlations (spatial, line-space) Mean of Group 1 Mean of Group 2 Group 2 Group 1 Source: Wikipedia SPIE Advanced Lithography 2008

  18. Unimodal Modeling Is Pessimistic • Conventional unimodal representation does not capture bimodalprocess variation • DPL modeling, analysis requirements = ? G1 G2 BC of G1 WC of G2 WC of G1 BC of G2 SPIE Advanced Lithography 2008

  19. Monte Carlo Simulation • SPICE model • 65nm, Typical corner (TT), 1.0V, 25C • SPICE circuit • 65nm NVT: Nominal CD is “60nm” • CD variation model • Assumption: small mean difference • Group1: N(meanG1=59nm, 3σ=5) • Group2: N(meanG2=61nm, 3σ=5) • Comparison • {Rise/Fall Delay, Leakage} of unimodal and bimodal distribution Unimodal Bimodal Group2 2n 64 66 59 61 54 56 60 Best CD Worst CD SPIE Advanced Lithography 2008

  20. rise fall Input 1 Input 0 Input 1 Input 0 rise fall Path Delay, Leakage (10K MC Iterations) • Bimodal distribution  two distinct simulation cases • DPL1: gate (2i+1) is in Group1 and gate (2i) is in Group2 • DPL2: gate (2i+1) is in Group2 and gate (2i) is in Group1 • Unimodal representation is too pessimistic • Different characteristics of DPL1 and DPL2  coloring affects timing SPIE Advanced Lithography 2008

  21. Severe Methodology Implications • Pervasive design flow changes • SPICE modeling to capture bimodal distribution ? • Cell characterization: multiple timing libraries for DPL1, DPL2 ? • Timing modeling based on actual placement and DPL mask coloring of each cell ? • New spatial correlation modeling (intra-exposure, transistor-level) ? • Note: • Path delay variation may actually decrease, but this cannot be exploited due to loss of spatial correlations SPIE Advanced Lithography 2008

  22. Outline • Two Cultures, Two Roadmaps • Lithography changes the Design roadmap • Design changes the Lithography roadmap • Toward a shared Litho-Design roadmap SPIE Advanced Lithography 2008

  23. 120 ITRS 2005 ITRS 2007 100 ~1.6 per node (based on device enhancement) 80 Frequency (GHz) 60 1.25per node (to meet power requirement) 40 20 0 2011 2015 2019 2021 2009 2013 2017 2007 Year 1. Power-Limited Frequency Roadmap • Power, thermal limits to maximum clock frequency (UCSD 2007) • ITRS MPU (HP) frequency roadmap updated in 2007 • Ripple effect  relaxed lithography CD 3 requirement ? Frequency Requirement Intrinsic Delay (CV/I) Requirement Physical Lgate Requirement CD Control Requirement SPIE Advanced Lithography 2008

  24. - 1 Tarrival 5 - 3 +2 1 Trequired 2 - 7 7 - 1 0 0 1 2 2 - 2 Gates of positive-slack cells can have larger CD variation budget! 0 1 0 1 - 5 5 2 - 4 +1 1 2 - 1 +2 0 2. Design Awareness: Slack • Positive timing slack can be exploited to reduce power and relax RET, litho requirements 3 1 4 Slack = Trequired – Tarrival CLK CLK SPIE Advanced Lithography 2008

  25. Design Awareness: Redundancy • Redundant features require less pattern fidelity • Implications • RET complexity, inspection + defect disposition flows • Reduced impact of process variability on design Non-Tree Routing (Loop) Metal Dummy Fill Redundant Via SPIE Advanced Lithography 2008

  26. 3. “Design For Equipment” • Systematic variation impacts  Mitigate or Exploit • OPC + fracturing: Major field, subfield boundary aware? • Overlay error: x- vs. y-direction bias of correction depending on circuit and layout? • Other: Model-based OPC error, CMP pattern-dependence • Example: ASML DoseMapper • APC: global CD uniformity in step-and-scan tool • Idea • Increase dose for timing-critical device  more speed • Decrease dose for non-critical device  less leakage • Two directions for optimization • Given cell placement, optimize the dose map • Given dose map, optimize the placement SPIE Advanced Lithography 2008

  27. Scan Direction Slit profile ASML DoseMapper • DoseMapper • Adjust exposure dose to improve CDU • Compensate ACLV and AWLV • Unicom (slit direction) • Change intensity profile across slit • Actuator: variable-profile gray filter • Maximum correction range: +/- 5% • Dosicom (scan direction) • Change intensity profile along scan direction • Dose profile can have higher-order corrections • Maximum correction range: +/- 5% • Dose Sensitivity • Linewidth has approximately linear relationship with exposure dose • E.g., dose sensitivity (DS): -2nm / % Adjust exposure dose Slit and Scan directions SPIE Advanced Lithography 2008

  28. Placement-Aware Dose Map • Same target CD for all devices • Leaves parametric yield improvement on the table • No “design awareness’’ UCSD (2007): different CDs Traditional: same CDs • Setup-timing critical device  larger dose  faster switching • Hold-timing critical device  smaller dose  less leakage • Improve timing yield without leakage penalty SPIE Advanced Lithography 2008

  29. Dose Map-Aware Placement • Given a dose map and a placement, swap critical cells to high-dose regions and non-critical cells to low-dose regions • Heuristic priorities based on (1) number of critical paths passing through cell, and (2) slacks of critical paths D1 Dose (D1) path P1 path P1 path P2 path P2 D2 Dose (D2) After Cell-Swapping Before Cell-Swapping Dose: D1<D2, Timing Criticality: P1>P2 SPIE Advanced Lithography 2008

  30. 10 x 10 20 x 20 20 x 50 Nom Lgate DMopt imp. (%) DMopt imp. (%) DMopt imp. (%) MCT (ns) 1.990 1.844 7.331 1.810 9.048 1.805 9.327 Pleakage (µW) 2430.2 2626.2 -8.066 2527.9 4.020 2433.6 0.138 Runtime -- 35.5 47.6 142.0 (s) Dose optimization results with different grids Example DoseMap Result (UCSD 2007) • Test case: TSMC90, ~20K standard cells • DoseMap Optimization: 9.3% cycle time improvement (0.13% leakage increase) • Essentially: near-maximum frequency gain, zero leakage penalty • DoseMap Optimization + dosePlace: 9.6% cycle time (0.2% leakage) Need roadmap of enablement SPIE Advanced Lithography 2008

  31. Outline • Two Cultures, Two Roadmaps • Lithography changes the Design roadmap • Design changes the Lithography roadmap • Toward a shared Litho-Design roadmap SPIE Advanced Lithography 2008

  32. More Than Moore: ITRS Consumer Stationary Driver 1000 48% CAGR Performance 100 30% CAGR # cores Normalized performance 14-17% CAGR Device speed 10 1 2014 2016 2018 2020 2012 2008 2006 2010 Why A Shared Roadmap? • Process: changes what is possible • Design: realizes what is possible • Neither by itself guarantees market success of ICs • Embedded software • Architecture • Stacked integration • … • “Dark Future” (2000 Japan DA Show keynote): electronics industry finds workarounds for both process and design If we do not hang together, we will surely hang separately -- Benjamin Franklin • If either is too risky or expensive  neither wins SPIE Advanced Lithography 2008

  33. Goal: Principled Connections Litho and RET metrics Electrical and Design metrics Layout practices and design rules • Balanced technology requirements • Balanced R&D investments “Shared Red Bricks” • Example: Line End Taper SPIE Advanced Lithography 2008

  34. Which Shape Is Best For Design? Moderate Aggressive Poly (b) Slope Best DOF (c) Bulge Worst DOF (a) Typical (d) Asymmetry Active SPIE Advanced Lithography 2008

  35. Line-End Shortening LW0 Line-End Bridging LEG Line-End Tapering • Tapering • A gradual lessening of width towards one end • We use the word “taper(ing)” to describe the shape of a polysilicon line-end • Traditional Taper Metric • Make as rectangular as possible, meeting line-end gap (LEG) and line-width (LW0) rules SPIE Advanced Lithography 2008

  36. Superellipse-Based Shape Model • “Academic” basis for shape modeling (UCSD 2007) • Superellipse • Parameters of superellipse • LEE: b’= b-c+k • a: gate length = size of 2*a • n: ‘roundness’ of superellipse • k: shift in y-direction (Bulge) •  : rotation (Asymmetry) y b x a Diffusion Gate y c b’  o a x o k (a) Bulge (b) Asymmetry SPIE Advanced Lithography 2008

  37. Increasing LEE Increasing Field Vth Cg misalignment Electrical Impact of Line-End Extension • Line-end extension increases Cg • fringe capacitance between line-end extension and channel • Cg affect Vth, following Vth model equation. • Cg increase  Vth decrease • Cg decrease  Vth increase • Ion and Ioff are functions of Vth • Vth increase Ion, Ioff decrease • Vth decrease  Ion, Ioff increase • Misalignment error can make large difference in Ion and Ioff SPIE Advanced Lithography 2008

  38. Capacitance Modeling of LEE • LEE makes fringing fields to the channel • Fringing field weakens as distance increases Oxide Gate on channel Gate on LEE ti Ctaper,i hi Poly li Cedge Active tox Active Poly Side view 3D view SPIE Advanced Lithography 2008

  39. i i i * From DaVinci + + 0 0 0 channel channel channel Incremental current due to top LEE Current without LEE effect Incremental current due to bottom LEE i 0 80nm fixed 80nm fixed Diffusion channel … … s=1 s=3 s=N s=2 s=N-1 Varied: 10, 40, 60nm 70nm fixed Gate Diffusion Location-Based Current Model • LEE affects current (Ion and Ioff) at gate edge • As LEE area increases, current at gate edge increases sharply. Increase depends on Ctaper SPIE Advanced Lithography 2008

  40. x y - k n n + = 1 a b - c Electrical Difference  Geometric Difference y Drawn Gate • Must consider electrical impact of shape • Lithographers prefer rectangular shapes with sharp edges • This comes at cost of litho + RET complexity • Is there a sweet spot? b Large ‘n’ x o a Diffusion Small ‘n’ Gate SPIE Advanced Lithography 2008

  41. Large ‘n’ Small ‘n’ Small ‘n’ Large ‘n’ Example: LEE Rule vs. Bitcell Leakage • LEE shape changes LEE length vs. Ioff relationship • Sweep LEE and ‘n’ of super-ellipse, measure Ioff Based on taper shape, LEE can be optimized to reduce bitcell size SPIE Advanced Lithography 2008

  42. Summary • Two Cultures, Two Roadmaps • Increasingly linked • Lithography changes the Design roadmap • Inevitable RDRs: sooner than later • DPL: new layout and analysis technology requirements • Design changes the Lithography roadmap • Macro effects: frequency  Lgate  3 • Design awareness • Design for Equipment • Toward a shared Litho-Design roadmap • Compelling motivation: Looming workarounds • Let’s get to work !!! SPIE Advanced Lithography 2008

  43. THANK YOU! SPIE Advanced Lithography 2008

  44. Tearing ITRS-Lithography Roadmap • CD tolerance is major factor of impacting power/timing variability for 65nm and below • Developing design methods that overcome variability requires reasonably accurate CD tolerance estimates • Problem in current ITRS-litho roadmap • No breakdowns for across field, across wafer, across lot, etc • No breakdowns for random, systematic • No breakdowns for detailed systematic factors • Gate CD control includes errors from all sources due to masks, imperfect OPC, ET/DOF, and resist and all spatial length scales (across field, across wafer, between lots) • We need to make sure we are being realistic in terms of what tolerances we quote, and what type of layout they are predicted for SPIE Advanced Lithography 2008

  45. ACLV CD Tolerance Factors in Litho Roadmap • Only ACLV CD tolerance extracted using detrating factor • Set 80% derating factor for ACLV (α=80%, β=10%, λ=10%) • All tolerance factors are not in roadmap • Litho-roadmap needs to show other systematic factors (proximity, ET/DOF, etc) ACLV = Across Chip Linewidth Variation ACWV = Across Wafer Linewidth Variation ALLV = Across Lot Linewidth Variation SPIE Advanced Lithography 2008

  46. LGATE Tolerance Computation from 2005 ITRS 2005 2006 2007 2008 2009 2010 2011 2012 2013 Table 69a MPU gate length (nm) 32 28 25 23 20 18 16 14 13 Table 77a LER (3 sigma) (nm) 4.2 3.8 3.4 3 2.7 2.4 2.1 1.9 1.7 Table 78a Gate CD control (3 sigma) (nm) 3.3 2.9 2.6 2.3 2.1 1.9 1.7 1.5 1.3 Overlay (3 sigma) (nm) 15 13 11 10 9 8 7 6 6 Mask magnification 4 4 4 4 4 4 4 4 4 MEEF - isolated lines 1.4 1.4 1.6 1.8 2 2.2 2.2 2.2 2.2 CDU - isolated (3 sigma) (nm) 3.8 3.4 2.6 2.1 1.7 1.3 1.2 1.1 1 MEEF - dense lines 2 2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 CDU - dense (3 sigma) (nm) 7.1 6 4.8 4.3 3.8 3.4 3 2.7 2.4 Linearity (nm) 13 11 10 9 8 7.2 6.4 5.6 5.1 CD mean to target (nm) 6.4 5.6 5.2 4.6 4 3.6 3.2 2.8 2.6 Calculations CDU - isolated lines (3 sigma) (nm) 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 CDU- dense (3 sigma) (nm) 0.4 0.3 0.3 0.2 0.2 0.2 0.2 0.1 0.1 Linearity + mean to target (nm) 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.3 0.2 derated overlay (3 sigma) (nm) 1.2 1.0 0.9 0.8 0.7 0.6 0.6 0.5 0.5 mask/proximity/exposure/DOF/resist 2.2 2.0 1.8 1.6 1.4 1.3 1.2 1.0 0.9 rss of the systematic numbers (nm) 2.3 2.0 1.9 1.6 1.5 1.4 1.2 1.1 0.9 % of physical gate length 8 8 8 8 8 8 9 9 8 plus the random variations (nm) 2.6 2.3 2.1 1.8 1.7 1.5 1.4 1.2 1.0 Extract CD Tolerance from Litho Roadmap • Systematic/random variations are divided • Each factor is divided by the derating factor •  help designer who tries to reduce CD tolerance of each factor SPIE Advanced Lithography 2008

  47. Require More Metrics in ITRS DFM Roadmap DFM Roadmap • Lithography (DPL) • Difference of mean • CD variability for each process • Vth variability for each process • Other metric for design • % area of redundancy circuit • Variability of difference between low- and high-Vth • DFM Tool • Requires DFM tool metric • Accuracy should be supported by ITRS-Modeling • Fast simulation in circuit level is also required as well as accuracy Modeling Roadmap Accuracy CD (photo/etch) prediction Process Junction depth Topography estimation Ion/Ioff accuracy Device Long-channel Vt Vt rolloff Circuit delay Circuit I-V error Parasitic C-V SPIE Advanced Lithography 2008

  48. Guardbands: Inevitable? At What Cost? Performance • Process change: O(weeks) • Design change: O(days-months) • But takes O(months) to assess in silicon • Design tweak to fit process : impossible • Process tweak to fit design : what we do today • SPICE, RCX models are fixed  guardbands inevitable • What is the cost of guardbands to the design? Technology Node SPIE Advanced Lithography 2008

  49. Design Timing Analysis Original Dose map Dose map Opt. Delay Cell Library Dose Map Optimal Dose map Timing Analysis Updated design Placement Optimized design Critical path Placement Opt. Timing and Leakage Optimization Flow • Dose Map opt • Input • Coeff calibration • Timing analysis • Dose map opt • Optimal dose map • Placement opt • Update design • Timing analysis • Critical path identification • Dose-aware place • Legalization • ECO routing SPIE Advanced Lithography 2008

More Related