Test Asynchronous FIR Filter Design. Presenter: Po-Chun Hsieh Advisor:Tzi-Dar Chiueh Date: 2003/12/1. Outline. Low Power Issue of Asynchronous Circuits Test FIR Design - Logic circuits - Multiplier - FIR Architecture Future work Conclusion Reference.
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Presenter: Po-Chun Hsieh
- Logic circuits
- FIR Architecture
( MR(n).t=“1”; MR(n).f=“0”; )
then the adder cell works
( MR(n).t=“0”; MR(n).f=“1”; )
then the adder cell will not work
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