Test Asynchronous FIR Filter Design. Presenter: Po-Chun Hsieh Advisor:Tzi-Dar Chiueh Date: 2003/12/1. Outline. Low Power Issue of Asynchronous Circuits Test FIR Design - Logic circuits - Multiplier - FIR Architecture Future work Conclusion Reference.
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
Test Asynchronous FIR Filter Design
Presenter: Po-Chun Hsieh
- Logic circuits
- FIR Architecture
( MR(n).t=“1”; MR(n).f=“0”; )
then the adder cell works
( MR(n).t=“0”; MR(n).f=“1”; )
then the adder cell will not work
 Grass, E. and S. Jones, "Activity-monitoring completion-detection (AMCD): a new approach to achieve self-timing", Electronics Letters, vol. 32, no. 2, pp. 86-88, January 1996
 Bartlett, V.A. and E. Grass, "Completion-detection technique for dynamic logic,"Electronics Letters, vol. 33, no. 22, pp. 1850-1852, October 1997.
Bartlett, V. A. and E. Grass, “A Self-Timed Multiplier using Condutional Evaluation", Proc. PATMOS'98, 8th International Workshop on Power, Timing, Modelling, Optimization and Simulation, Lyngby, Denmark, pp.429-438, October 1998
 D.Kearney and N.W.Bergmnn, “Bundled Data A syncheonous Multipliers with Data Dependent Computation Times”,Proc. ASYNC’97, 2nd Int.Symp. On Advanced Research in Asynchronous Circuits and Systems,pp. 186-197,1997
 Bartlett, V. A. and E. Grass, “A Low-Power Asynchronous VLSI FIR Filter", Proc. ARVLSI'01, 19th Conference on Advanced Research in VLSI, Salt Lake City, Utah, USA, March 2001.