Slide1 l.jpg
This presentation is the property of its rightful owner.
Sponsored Links
1 / 50

Chapter 6 PowerPoint PPT Presentation


  • 169 Views
  • Uploaded on
  • Presentation posted in: General

Chapter 6. Delay Testing. What is this chapter about?. Introduce delay test concepts, models, and test generation Provide overview of common delay test approaches Focus on Delay test application Delay fault models Test generation High quality delay tests. Introduction to Delay Testing.

Download Presentation

Chapter 6

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Slide1 l.jpg

Chapter 6

Delay Testing


What is this chapter about l.jpg

What is this chapter about?

  • Introduce delay test concepts, models, and test generation

  • Provide overview of common delay test approaches

  • Focus on

    • Delay test application

    • Delay fault models

    • Test generation

    • High quality delay tests


Introduction to delay testing l.jpg

Introduction to Delay Testing

  • Introduction

  • Delay Testing Approaches

  • Circuit and Delay Models

  • Delay Test Application

  • Transition Fault Test

  • Path Delay Test

  • Constrained Delay Test

  • Conclusions


Introduction l.jpg

Introduction

  • Goal of Delay Testing

    • Primary: Verify circuit timing (e.g. clock frequency) over supply voltage and temperature range

    • Secondary: Identify marginal circuits that meet specifications


Delay testing approaches 1 l.jpg

Delay Testing Approaches (1)

  • Random

    • Apply random patterns at rated clock speed

    • Advantages

      • Can generate patterns on-chip (BIST)

      • Applied as in normal operation

      • Fortuitous detection of unmodeled faults

    • Disadvantages

      • Poor coverage of long paths

      • Higher than normal circuit activity (power, noise)


Delay testing approaches 2 l.jpg

Delay Testing Approaches (2)

  • Functional

    • Apply functional patterns at rated clock speed

    • Advantages

      • Most accurate test

      • Chip operating in normal mode

      • Fortuitous detection of unmodeled faults

    • Disadvantages

      • Poor coverage, coverage difficult to compute

      • High test pattern development cost

      • High test application cost without large on-chip cache/memory


Delay testing approaches 3 l.jpg

Delay Testing Approaches (3)

  • Structural

    • Use delay fault models and circuit structure to generate tests

    • Advantages

      • Automatic test pattern generation

      • High fault coverage

      • Easier diagnosis

    • Disadvantages

      • Simplifying assumptions in delay fault model

      • Design for testability (DFT) required for high coverage

      • Test application very different than normal operation


Huffman sequential circuit model l.jpg

Primary Inputs (PI) x1, x2,…

Primary Outputs (PO) z1, z2,…

Pseudo Primary Inputs (PPI) y1, y2,…

Pseudo Primary Outputs (PPO) Y1, Y2,…

Huffman Sequential Circuit Model


Design assumptions l.jpg

Design Assumptions

  • Structural delay test of synchronous sequential digital circuits

    • Delay test of the logic circuits

      • Gate level primitives, including latches and flip-flops

    • Most flip-flops and latches are scanned

    • Embedded memory modeled as black boxes

      • Test them separately

  • Same assumptions used in most commercial ATPG tools


Circuit delay models 1 l.jpg

Circuit Delay Models (1)

  • Some delay fault models need circuit delays

  • Gate delay

    • Delay from gate input to output

    • Can have different delays for rising or falling transitions, different inputs to outputs

    • Interconnect delay lumped with gate

  • Gate transport delay

    • Gate delay without interconnect delay

  • Interconnect propagation delay

    • Separate delay to each net fanout (gate input)


Circuit delay models 2 l.jpg

Circuit Delay Models (2)

  • Inertial delay

    • Minimum pulse width that propagates through a gate

    • Used to analyze glitch generation and propagation

  • Min-max delay

    • Abstraction of process variation

    • Gate and interconnect delay correlations usually not available


Delay test application 1 l.jpg

Delay Test Application (1)

  • Launch transitions into circuit from PIs and PPIs (referred to collectively as PIs)

  • Capture circuit response at POs and PPOs (collectively POs) at specified time

  • Compare results with correct response

  • Two-pattern test

    • Required to launch transitions

    • First (initialization) vector initializes circuit

    • Second (test) vector launches transitions


Delay test application 2 l.jpg

Delay Test Application (2)

  • How to hold two test vectors in scan chains?

    • Enhanced scan – holding latch on output of flip-flop

      • Scan first vector in, transfer to holding latches, scan second vector in, enable on latches launches transitions

      • Expensive in area and delay, so uncommon

    • Launch-on-shift (LOS) – also known as skewed load, launch-off-shift

    • Launch-on-capture (LOC) – also known as broadside test, launch-off-capture


Transition fault model l.jpg

Transition Fault Model

  • Assumes a large/gross delay is present at a circuit node

    • Slow-to-rise (STR), slow-to-fall (STF)

  • Irrespective of which path the effect is propagated, the gross delay defect will be late arriving at an observable point

  • Most commonly used in industry

    • Simple and number of faults linear to circuit size

    • Also needs 2 vectors to test

  • Node x slow-to-rise (x-STR) can be modeled simply as two stuck-at faults

    • First time-frame: x/1 needs to be excited

    • Second time-frame: x/0 needs to be excited and propagated


Launch on shift approach l.jpg

Launch-on-Shift Approach

Last scan-in shift cycle

Launch cycle

Capture cycle

1

Scan enable

Scan-in

0

A

Combinational Circuit

1

B

Scan-out


Launch on shift approach16 l.jpg

Launch-on-Shift Approach

Last scan-in shift cycle

Launch cycle

Capture cycle

1

Scan enable

0

A

Combinational Circuit

1

B


Launch on shift approach17 l.jpg

Launch-on-Shift Approach

Last scan-in shift cycle

Launch cycle

Capture cycle

Scan enable

Scan-in

1

A

Combinational Circuit

0

B

Scan-out


Launch on shift approach18 l.jpg

Launch-on-Shift Approach

Last scan-in shift cycle

Launch cycle

Capture cycle

Scan enable

Scan-in

1

A

Combinational Circuit

0

B

Scan-out


Launch on capture approach l.jpg

Launch-on-Capture Approach

Last scan-in shift cycle

Launch

Capture

Dummy cycle

Scan enable

Scan-in

0

A

Combinational Circuit

1

B

Scan-out


Launch on capture approach20 l.jpg

Launch-on-Capture Approach

Last scan-in shift cycle

Dummy cycle

Launch

Capture

Scan enable

Scan-in

0

0

A

Combinational Circuit

1

0

B

Scan-out


Launch on capture approach21 l.jpg

Launch-on-Capture Approach

Last scan-in shift cycle

Launch

Capture

Dummy cycle

Scan enable

Scan-in

0

0

A

Combinational Circuit

0

1

B

Scan-out


Launch on capture approach22 l.jpg

Launch-on-Capture Approach

Last scan-in shift cycle

Launch

Capture

Dummy cycle

Scan enable

Scan-in

0

A

Combinational Circuit

0

B

Scan-out


Launch on shift implication l.jpg

1X

X0

Launch-on-Shift Implication

Scan-in

A

Combinational Circuit

B

C

Scan-out


Launch on capture implication l.jpg

1X

X0

Launch-on-Capture Implication

Scan-in

A

Combinational Circuit

B

C

Scan-out


Test robustness l.jpg

Test Robustness

  • Robust test

    • Detects delay fault independent of circuit delays

  • Nonrobust test

    • Detection depends on circuit delays

  • Functionally sensitizable test

    • Detection depends on delays on multiple paths


Robustness examples l.jpg

Robustness Examples

Nonrobust

Robust

0

Functionally Sensitizable


Transition fault test example l.jpg

0 0 x1

0 1 x2

v2v1

1 1 x3

3

y

2

2

3

t=0

t=2

t=7

Transition Fault Test Example


Transition fault properties l.jpg

Transition Fault Properties

  • A transition fault may be launched robustly, non-robustly, or neither

  • Example: STR at output of OR gate


Transition fault properties cont l.jpg

Transition Fault Properties (cont.)

  • A transition fault may be propagatedrobustly, non-robustly, or neither

  • Example: STF at output of gate a


Untestable transition fault l.jpg

a

d

b

c

Untestable Transition Fault

  • STF on signal d is untestable under Launch on Shift

    • Second vector needs to be abc=000

    • First vector must then be abc=00X


Path length comparison robust l.jpg

Path Length Comparison (Robust)


Transition fault testing with stuck at atpg l.jpg

Transition Fault Testing with Stuck-At ATPG

  • Simply treat each transition fault as two stuck-at faults

  • Node x slow-to-rise (x-STR) can be modeled simply as two stuck-at faults

    • First time-frame: x/1 needs to be excited

    • Second time-frame: x/0 needs to be excited and propagated

    • Use x/0 and x/1 for x-STF

  • Apply LOC or LOS constraints in ATPG as needed


Path delay testing l.jpg

Path Delay Testing

  • Path Delay Fault

    • Delay distributed along path

      • Could be combination of slow process and spot defects

    • Classic model

      • Any path could have any delay

      • Must test all paths

      • But infeasibly large number of paths – exponential in circuit size

    • KLPG – K Longest Paths Per Gate

      • Test K longest paths through each line, with both rising and falling transition on the line

      • Linear in circuit size


Test generation algorithm l.jpg

Test Generation Algorithm

Search space

Scan cells

Scan cells

Constraints from outside search space


Path generation flow l.jpg

Start

Insert into the partial path store

Extend the partial path with longest potential delay

Apply heuristics to avoid false paths

Apply side inputs and perform direct implications

N

Y

N

Conflict?

Complete path?

Y

End

Final justification

Path Generation Flow


Direct implication l.jpg

Conflict

0

1

Direct Implication

  • Detect local conflicts

  • Most conflicts are local


Heuristic forward trimming l.jpg

Heuristic – Forward Trimming

  • Trim non-solution space immediately

  • Path generation is guided to find a true path

    • Large saving if many paths in the logic block

Logic Block

gi

gj

1

1

0


Other heuristics l.jpg

Other Heuristics

  • Smart PERT

    • Computes the upper bound of longest testable path more accurately

  • Relations between gates and global longest path generation

    • A long path through a gate may be one of the K longest paths through another gate

    • Reduce repeated work


7 value algebra for partial scan l.jpg

7-Value Algebra for Partial Scan

x – Unknown u – Uncontrollable


7 value algebra for partial scan40 l.jpg

7-Value Algebra for Partial Scan

x – Unknown u – Uncontrollable


Application of 7 value algebra l.jpg

Application of 7-Value Algebra

M1

u

g1

n1

0/u

n3

x

M2

g2

0/u

x

n2

n5

n4


Application of 7 value algebra42 l.jpg

Application of 7-Value Algebra

M1

u

g1

n1

0/u

n3

x

M2

g2

0/u

x

n2

n5

n4


Final justification l.jpg

1

1

1

1

Final Justification

  • Detect global conflicts which cannot be detected by direct implication

  • Find the vector pair which sensitizes the path

    • PODEM/FAN based justification algorithm


Klpg 1 test set construction l.jpg

KLPG-1 Test Set Construction

Non-robust

test

Robust test

Long

transition

fault test

A long transition fault test tests longer paths than a regular transition fault test


Pseudo functional testing l.jpg

Pseudo-Functional Testing

  • Avoids over-testing by scanning in non-functional states

    • Does not induce excessive circuit switching

    • Does not exercise functionally infeasible paths

      • a timing failure due to a functionally infeasible path may not be a true failure and will result in throwing good parts away

    • Avoid Yield loss


Constrained atpg l.jpg

a

x

b

c

y

d

Constrained ATPG

  • To avoid scanning in functionally unreachable states, constraints can be used

  • Let (¬x + y) represent a constraint

    • then abcd={1000, 0100, 1100, 1001, 0101, 1101, 1010, 0110, 1110} are the illegal states


Pair wise constraints l.jpg

Pair-wise Constraints

  • Compute constraints via logic implications

  • Implications for g=0 and g=1 over the time window -t to t (t is user-specified) are first computed and stored

  • Apply transitive law to identify those implications in the 0th time frame

    • a implies b (next time-frame), b implies c (previous time-frame), then a implies c (same time-frame)

    • Remove all combinational implications

  • Resulting set are functional constraints


Multi literal constraints l.jpg

Multi-Literal Constraints

  • [A=1] Λ [B=1]  [F=0] in the next time-frame.

  • Key: identify x  A (prev time frame) and y  B (prev time frame), then we have (x Λ y)  [F=0] in the same time-frame


Constrained atpg49 l.jpg

Constrained ATPG

  • Given a set of computed constraints, U

  • ATPG must not violate any constraint in U during the search

  • Key: want U to be as comprehensive as possible


Alternative approach to pseudo functional testing l.jpg

Alternative Approach to Pseudo-Functional Testing

  • Run ATPG without any constraints

  • Map each generated pattern to a known valid state

  • Must make sure the modification still detects the target fault

    • May need to try mapping to different valid states


  • Login