Timing-Driven Placement for Heterogeneous FPGA. Bo Hu Velogix Inc. ICCAD 06. Outline. Introduction Problem Multi-layer Density System Timing-Driven Placement Experiments Conclusions. Introduction.
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It consists of two-dimension array of Basic Process Unit(BPU).
Each BPU contains a two-dimension array of LUTs, a computing unit(CU) and a memory block.
Large CU geometric shape forms blockage for memory blocks and LUTs.
Small CU geometric shape cause congestion.
A group of CU components might be closely located in some local region where there are not enough CU resources available.
d(b): density at bin b.
A(b,n): the intersection area between b and node n.
A(b): the area of bin b.
Wp[ j ] and Wp[ j-1 ] is the weight for connection p at jth and jth-1 expansion.
f[ j ] is the adjustment factor at jth expansion.
f0[ j ] : the preset maximum adjustment factor at jth iteration. f0[ 0]=1 and gradually approaches to zero.
Sp : timing slack on connection p.
Sworst : the worst slack.
ε : a preset value used to decide whether a connection is critical.
lp : the current length of connection p.
lpmin and lpmax : the minmum and maxmum length of p.