Improved design of high performance parallel decimal multipliers
Download
1 / 13

Improved Design of High-Performance Parallel Decimal Multipliers - PowerPoint PPT Presentation


  • 102 Views
  • Uploaded on

Improved Design of High-Performance Parallel Decimal Multipliers. Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Mar-9. Outline. Information of literature Background Decimal Coding

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' Improved Design of High-Performance Parallel Decimal Multipliers' - carsyn


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Improved design of high performance parallel decimal multipliers

Improved Design of High-Performance Parallel Decimal Multipliers

Han Liu

Supervisor: Seok-Bum Ko

Electrical & Computer Engineering Department 2010-Mar-9


Outline
Outline Multipliers

  • Information of literature

  • Background

  • Decimal Coding

  • Partial Product Generation

  • Multiplier Architecture

  • Partial Product Reduction

  • Comparison

  • Conclusion


Information of literature
Information of literature Multipliers

Improved Design of High-Performance Parallel Decimal Multipliers

Alvaro Vazquez, ElisardoAntelo, and Paolo Montuschi

IEEE TRANSACTIONS ON COMPUTERS 2009 Nov.


Background
Background Multipliers

  • Multiplication Operation

  • Parallel and Serial Multiplication

    • How to add the partial product together

    • Tradeoff of Area and Latency


Decimal coding
Decimal Coding Multipliers

Fast ×5 and ×2 with coding conversion (no carry propagation)

N_5211 × 2 (LS2) = 2N_4221

N_4221 × 5 (LS3) = 5N_5211


Partial product generation 1 3
Partial Product Generation Multipliers1/3

For calculating X10 × Y10, we need {0, X, 2X, 3X, … , 9X}, this is called partial product

SD Radix-10: convert Decimal set {0,…,9} to SD set {-5,…,0,…,5}, then

Only {0, X, 2X, 3X, 4X, 5X} are needed to be implemented.

SD Radix-5: Y=5 × YU+ YL, then

Only YU set {0, 5X, 10X} and YL set {-2X, -X, 0, X, 2X} are needed to be implemented.


Partial product generation 2 3
Partial Product Generation Multipliers2/3

Radix-5 PP Generation


Partial product generation 3 3
Partial Product Generation Multipliers3/3

Radix-10 SD PP Generation


Multiplier architecture
Multiplier Architecture Multipliers

Radix-10 Parallel Multiplier

Radix-5 Parallel Multiplier



Comparison
Comparison Multipliers

[9] L. Dadda

[20] T. Lang

[12 13 19] M. J. Schulte


Conclusion
Conclusion Multipliers

  • SD radix-10 and radix-5 parallel multiplication are interesting option for higher performance with moderate area

  • For higher performance the choice is the SD radix-5 architecture, although both designs have very close figures.


Question
Question Multipliers

Thanks!


ad