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Reconfigurable Systems - Conceptual Design Review. Reconfigurable Systems. Team Chris Canine Terseer Ityavyar Cameron D. Dennis Client / Faculty Mentor Dr. Greg Donohoe Lead Instructor Dr. Joe Law Graduate Mentor John Geidl Sponsor NASA UI CAMBR. Background. Embedded Computing.

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Reconfigurable systems
Reconfigurable Systems

  • Team

    • Chris Canine

    • Terseer Ityavyar

    • Cameron D. Dennis

  • Client / Faculty Mentor

    • Dr. Greg Donohoe

  • Lead Instructor

    • Dr. Joe Law

  • Graduate Mentor

    • John Geidl

  • Sponsor

    • NASA

    • UI CAMBR



Embedded computing
Embedded Computing

  • Invisible to the user

    • Example: The modern day vehicle has about 40 microprocessors

  • Goal: High speed with smallest footprint

    • Small footprint

      • Size

      • Weight

      • Power consumption

    • Speed (computing power)

  • Linear system

    • Computing is done logically

    • Resources take up memory


Reconfigurable computing system

Input

PE2

PE0

PE1

IOP0

Output

FireIOP0

PE4

IOP1

FirePE0

FirePE2

FirePE3

FirePE1

FirePE3

PE3

FireIOP1

Reconfigurable Computing System

  • Massive data path parallelism

  • Do many tasks at once

  • Flexibility is gained through reconfiguration

    • Processing Elements (PE’s)

    • Interconnect


Reconfigurable interconnect
Reconfigurable Interconnect

  • Current technology uses shared, parallel buses

    • Limited throughput with high power consumption

  • Proposed technology uses dedicated, serial data paths with crossbar switching

    • Very high throughput

    • Low power consumption

Crossbar Switching

Picture from National Semiconductor’s “LVDS Owner’s Manual”


Last year s s d project

Configurable Memory Module

Configurable Memory Module

Control

Interconnect

Interconnect

Global Clock

Processor Node

Processor Node

Last Year’s S.D. Project


Strategy
Strategy

ULP 0.5V

ULP 0.5V

LVCMOS 2.5V

LVCMOS 2.5V

LVCMOS

Data source

Data sink

LVDS

LVDS

XBAR

Data sink

serializer

Data source

deserializer

LVDS

XBAR

serializer

Data sink

deserializer

Data source

Data source

Data sink

  • Old approach

  • LVCMOS signals

  • Parallel routing

  • New approach

  • LVDS signaling

  • Serial routing


Low voltage differential signaling

‘0’

Sender

Receiver

ZL

‘1’

ZL

Low Voltage Differential Signaling

  • How it works:

    • Switch current direction

    • Input current sense detection

  • Routing:

    • Dedicated forward and return signal lines

    • Tailored transmission line characteristics, field cancellation

    • Minimize frequency effects, reflection and signal distortion


Low voltage differential signaling1
Low Voltage Differential Signaling

  • Noise sensitivity:

    • Reduced crosstalk

    • Robust, excellent common-mode noise rejection

    • Low voltage (350 mV), higher frequencies (>1.5 GHz)

    • Smaller voltage swings

  • Power consumption:

    • Lower, relatively independent of switching frequency

    • To minimize power per bit, maximize data rate through each serial channel

2.5

0

Standard CMOS

+0.175

-0.175

LVDS



Our goal
Our Goal

  • To compare serial communication versus parallel communication

  • Show that Low Voltage Differential Signaling (LVDS) communication is a viable implementation method

  • Highlight the benefits of LVDS including

    • High-speed data transfer

    • Lowered Electro-Magnetic Interference (EMI)

    • Low power consumption

    • Reduced circuit board area


Needs
Needs

  • A study that will

    • Convince a spacecraft system engineer to use serial LVDS designs for reconfigurable systems

    • Provide the documentation to allow the implementation of serial LVDS designs


Constraints
Constraints

  • No slower than 800 data Mbits per second

  • Variable path delay

  • Function with different delays in the communication path

  • No errors detected in a bit error rate test (BERT) in 15 minutes of continuous operation

  • Preferred all on one printed circuit board


Specifications
Specifications

  • Proof of concept

    • Compare differential, sequential communication vs. single-ended, parallel communication.

    • Power consumption – “Gigahertz @ milliWatts”

      • Reduced watts per bit

    • Circuit board area – Show a greatly reduced area vs. parallel system


Specifications cont
Specifications (cont.)

  • Two Source Nodes

  • Two Destination Nodes

    • Transmit from either source to either destination depending on a specific control signal sent to switch the central crosspoint switch

  • Desirable

    • Go to two destinations from one source

    • Full bidirectional communication


Deliverables
Deliverables

  • Reports

    • Compare serial vs. parallel implementations for power and area

    • Describe a design flow using the Cadence Tools

    • Proper documentation to pass on to someone else to duplicate the design


Deliverables cont
Deliverables (cont.)

  • Hardware

    • Demo a working serial system meeting the specifications above

    • Instrument as necessary to demonstrate the specifications

      • Measure and report Bit Error Rate (BERT)

      • Measure and report power consumption



Components needed
Components Needed

  • 4 Field Programmable Gate Arrays (FPGA)

  • 4 Serializer/Deserializer’s (SerDes)

  • 1 Crosspoint Switch (XBAR)

  • LCD Displays


Option a

FPGA

FPGA

FPGA

FPGA

SER

SER

DES

DES

XBAR

Option A

  • Offboard FPGA

  • Onboard SerDes

  • Can use D2SB & DIO5

    • Already assembled

    • Easy setup

    • LCD included

    • Relative low cost

    • Will reduce Speed

    • Complicated pinout


Option a specifics
Option A Specifics

  • Offboard FPGA

    • Digilent D2SB/DIO5 Kit with Xilinx Spartan IIE FPGA

  • Onboard SerDes

    • National Semiconductor DS92LV18

  • Onboard Crosspoint Switch

    • National Semiconductor SCAN90CP02

  • Additional Onboard Hardware

    • LCD and other display hardware is included on the D2SB/DIO5 board


Option b

FPGA

FPGA

FPGA

FPGA

SER

SER

DES

DES

XBAR

Option B

  • Onboard FPGA’s

  • Onboard SerDes

    • SerDes will allow faster onboard communications

    • Less noise / interference

    • Smaller board area

    • Requires more components

    • Complicated layouts and chip placements


Option b specifics
Option B Specifics

  • Onboard FPGA

    • Xilinx Spartan IIE FPGA

  • Onboard SerDes

    • National Semiconductor DS92LV18

  • Onboard Crosspoint Switch

    • National Semiconductor SCAN90CP02

  • Additional Onboard Hardware

    • LCD to display BERT results


Option c
Option C

  • Onboard FPGA’s

  • Use built-in SerDes capability of FPGA’s

    • Least amount of components

    • More difficult VHDL implementation

    • FPGA with these abilities is very expensive

    • Less interconnect = less noise introduction

    • Smallest board size

FPGA

FPGA

XBAR

FPGA

FPGA


Option c specifics
Option C Specifics

  • Onboard FPGA

    • Xilinx Virtex Family FPGA

  • Onboard SerDes

    • None Required

  • Onboard Crosspoint Switch

    • National Semiconductor SCAN90CP02

  • Additional Onboard Hardware

    • LCD to display BERT results


Our recommendation option b
Our Recommendation - Option B

  • Reduced cost

  • Ease of implementation

  • All on one printed circuit board


Projected costs
Projected Costs

  • 4 x FPGA

    • Xilinx Spartan IIE FPGA - $50.00

  • 1 x Crosspoint Switch

    • National Semiconductor SCAN90CP02 - $5.00

  • 4 x Serializer / Deserializer

    • National Semiconductor DS92LV18 - $16.50

  • LCD and Misc. Connectors - $50.00

  • Printed Circuit Board Fabrication - $250.00

  • Total Projected Cost: $571.00





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