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332:479 Concepts in VLSI Design Lecture 6 CMOS Transistor TheoryPowerPoint Presentation

332:479 Concepts in VLSI Design Lecture 6 CMOS Transistor Theory

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### 332:479 Concepts in VLSIDesignLecture 6 CMOS Transistor Theory

David Harris and Michael Bushnell

Harvey Mudd College and Rutgers University

Spring 2004

Outline

- Introduction
- MOS Capacitor
- nMOS I-V Characteristics
- pMOS I-V Characteristics
- Gate and Diffusion Capacitance
- Pass Transistors
- RC Delay Models
- Adjustments for non-ideal 2nd-order effects
- Small-signal MOSFET model

Material from: CMOS VLSI Design,

by Weste and Harris, Addison-Wesley, 2005

Concepts in VLSI Des. Lec. 6

Introduction

- So far, we have treated transistors as ideal switches
- An ON transistor passes a finite amount of current
- Depends on terminal voltages
- Derive current-voltage (I-V) relationships

- Transistor gate, source, drain all have capacitance
- I = C (DV/Dt) -> Dt = (C/I) DV
- Capacitance and current determine speed

- Also explore what a “degraded level” really means

Concepts in VLSI Des. Lec. 6

MOS Characteristics

- MOS – majority carrier device
- Carriers: e-- in nMOS, holes in pMOS
- Vt– channel threshold voltage (cuts off for voltages < Vt)

Concepts in VLSI Des. Lec. 6

nMOS Enhancement Transistor

- Moderately doped p type Si substrate
- 2 Heavily doped n+ regions

Concepts in VLSI Des. Lec. 6

I vs. V Plots

- Enhancement and depletion transistors
- CMOS – uses only enhancement transistors
- nMOS – uses both

Concepts in VLSI Des. Lec. 6

Materials and Dopants

- SiO2 – low loss, high dielectric strength
- High gate fields are possible

- n type impurities: P, As, Sb
- p type impurities: B, Al, Ga, In

Concepts in VLSI Des. Lec. 6

Bipolar vs. MOS

- Bipolar – p-n junction – metallurgical
- MOS
- Inversion layer / substrate junction field-induced
- Voltage-controlled switch, conducts when VgsVt
- e-- swept along channel when Vds > 0 by horizontal component ofE
- Pinch-off – conduction by e–- drift mechanism caused by positive drain voltage
- Pinched-off channel voltage:Vgs – Vt(saturated)
- Reverse-biased p-n junction insulates from the substrate

Concepts in VLSI Des. Lec. 6

JFET vs. FET Transistors

- Junction FET (JFET) – channel is deep in semiconductor
- MOSFET – For given Vds & Vgs,Ids controlled by:
- Distance between source & drain L
- Channel width W
- Vt
- Gate oxide thickness tox
- e gate oxide
- Carrier mobility m

Concepts in VLSI Des. Lec. 6

JFET Transistor

Concepts in VLSI Des. Lec. 6

MOS Capacitor

- Gate and body form MOS capacitor
- Operating modes
- Accumulation
- Depletion
- Inversion

Concepts in VLSI Des. Lec. 6

Terminal Voltages

- Mode of operation depends on Vg, Vd, Vs
- Vgs = Vg – Vs
- Vgd = Vg – Vd
- Vds = Vd – Vs = Vgs - Vgd

- Source and drain are symmetric diffusion terminals
- By convention, source is terminal at lower voltage
- Hence Vds 0

- nMOS body is grounded. First assume source is 0 too.
- Three regions of operation
- Cutoff
- Linear
- Saturation

Concepts in VLSI Des. Lec. 6

nMOS Linear

- Channel forms
- Current flows from d to s
- e- from s to d

- Ids increases with Vds
- Similar to linear resistor
- At drain end of channel, only difference between gate & drain voltages effective for channel creation

Concepts in VLSI Des. Lec. 6

nMOS Saturation

- Channel pinches off
- Ids independent of Vds
- We say current saturates
- Similar to current source

Concepts in VLSI Des. Lec. 6

I-V Characteristics

- In Linear region, Ids depends on
- How much charge is in the channel?
- How fast is the charge moving?

Concepts in VLSI Des. Lec. 6

Channel Charge

- MOS structure looks like parallel plate capacitor while operating in inversion
- Gate – oxide – channel

- Qchannel =

Concepts in VLSI Des. Lec. 6

Channel Charge

- MOS structure looks like parallel plate capacitor while operating in inversion
- Gate – oxide – channel

- Qchannel = CV
- C =

Concepts in VLSI Des. Lec. 6

Channel Charge

- MOS structure looks like parallel plate capacitor while operating in inversion
- Gate – oxide – channel

- Qchannel = CV
- C = Cg = eoxWL/tox = CoxWL
- V =

Cox = eox / tox

Concepts in VLSI Des. Lec. 6

Channel Charge

- MOS structure looks like parallel plate capacitor while operating in inversion
- Gate – oxide – channel

- Qchannel = CV
- C = Cg = eoxWL/tox = CoxWL
- V = Vgc – Vt = (Vgs – Vds/2) – Vt

Cox = eox / tox

Concepts in VLSI Des. Lec. 6

Carrier velocity

- Charge is carried by e-
- Carrier velocity v proportional to lateral E-field between source and drain
- v =

Concepts in VLSI Des. Lec. 6

Carrier Velocity

- Charge is carried by e-
- Carrier velocity v proportional to lateral E-field between source and drain
- v = mE m called mobility
- E =

Concepts in VLSI Des. Lec. 6

Carrier Velocity

- Charge is carried by e-
- Carrier velocity v proportional to lateral E-field between source and drain
- v = mE m called mobility
- E = Vds/L
- Time for carrier to cross channel:
- t =

Concepts in VLSI Des. Lec. 6

Carrier Velocity

- Charge is carried by e-
- Carrier velocity v proportional to lateral E-field between source and drain
- v = mE m called mobility
- E = Vds/L
- Time for carrier to cross channel:
- t = L / v

Concepts in VLSI Des. Lec. 6

nMOS Linear I-V

- Now we know
- How much charge Qchannel is in the channel
- How much time t each carrier takes to cross

Concepts in VLSI Des. Lec. 6

nMOS Linear I-V

- Now we know
- How much charge Qchannel is in the channel
- How much time t each carrier takes to cross

Concepts in VLSI Des. Lec. 6

nMOS Linear I-V

- Now we know
- How much charge Qchannel is in the channel
- How much time t each carrier takes to cross

Concepts in VLSI Des. Lec. 6

nMOS Saturation I-V

- If Vgd < Vt, channel pinches off near drain
- When Vds > Vdsat = Vgs – Vt

- Now drain voltage no longer increases current

Concepts in VLSI Des. Lec. 6

nMOS Saturation I-V

- If Vgd < Vt, channel pinches off near drain
- When Vds > Vdsat = Vgs – Vt

- Now drain voltage no longer increases current

Concepts in VLSI Des. Lec. 6

nMOS Saturation I-V

- If Vgd < Vt, channel pinches off near drain
- When Vds > Vdsat = Vgs – Vt

- Now drain voltage no longer increases current

Concepts in VLSI Des. Lec. 6

Example

- We will be using a 0.6 mm process for your project
- From AMI Semiconductor
- tox = 100 Å
- m = 350 cm2/V*s
- Vt = 0.7 V

- Plot Ids vs. Vds
- Vgs = 0, 1, 2, 3, 4, 5
- Use W/L = 4/2 l

Concepts in VLSI Des. Lec. 6

pMOS I-V

- All dopings and voltages are inverted for pMOS
- Mobility mp is determined by holes
- Typically 2-3x lower than that of electrons mn
- 120 cm2/V*s in AMI 0.6 mm process

- Thus pMOS must be wider to provide same current
- In this class, assume mn / mp = 2

Concepts in VLSI Des. Lec. 6

Summary

- Current Characteristics of MOSFET
- Calculation of VtandImportant 2nd-Order Effects
- Small-Signal MOSFET Model
- Models in this lecture
- For pedagogical purposes only
- Obsolete for deep-submicron technology
- Real transistor parameter differences:
- Much higher transistor current leakage
- Body effect less significant than predicted
- Vt is lower than predicted

Concepts in VLSI Des. Lec. 6

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