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Status of GTK ASIC - TDCpix

Status of GTK ASIC - TDCpix. 22 Nov 2011 G. Aglieri, M. Fiorini, P. Jarron, J. Kaplon, A. Kluge, E. Martin, M. Noy, L. Perktold, K. Poltorak. TDCpix ASIC block diagram (60 bit serial/4 LVDS pairs parallel). 45. April 2, 2012. 4x45. 45. 2.7 /4 Mhits/s. Config pixel. 5 bit trimDAC.

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Status of GTK ASIC - TDCpix

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  1. Status of GTK ASIC - TDCpix 22 Nov 2011 G. Aglieri, M. Fiorini, P. Jarron, J. Kaplon, A. Kluge, E. Martin, M. Noy, L. Perktold, K. Poltorak

  2. TDCpix ASIC block diagram (60 bit serial/4 LVDS pairs parallel) 45 April 2, 2012 4x45 45 2.7 /4 Mhits/s Config pixel 5 bittrimDAC pixel driver&line&receiver pixel cell x 45 pixel column double column 0 column 1 double column 5 double column 4 double column 3 double column 1 double column 6 double column 2 double column 19 end of column 5 2, parallel_load&daq_rdy hitArbiter 0 & edge detector hA 1 hA 8 hA 2 column 0 1,hit 32 clkdll=320MHz coarseTimeStamp DLL fineHitRegister 0 coarseHitRegister 0 DLL 0 2 x 32 2 x (13 + 5) 5 add+5 pil serialTime state machine 12 1 > CP&PD clksync or clkserialTime syncRegister 2 x 32 2 x (13 + 5) 5 add+5 pil clkdll coarseTimeStampServer0 > 9 fineTimeStampEncoder coarseTimeStampEncoder group EOC 1 group EOC 2 group EOC 8 group EOC 0 5 rise+5 trail 13 rise+5 trail 5 address + 5 pileup 32 fineRise 32 fineTrail 2x12+1 coarseRise 2x4+1 coarseTrail 5 fineRise 5 fineTrail 12+1 coarseRise6+1 coarseTrail 2 group collision > clksync 0.3/0.44 Mhit/s pixelGroupFifo (depth= 3) 648 FF @ 2 depth 8 bit thresholdDACcolumn & 3 bit bias DAC 42 42 5 rise+5trail+12+1 rise+6+1 trail+5add+5pil+2col=42 42 columnMux 9 to 1 23 cell units * (0.40 µmx 4.8 µm)* (648+152+373/10) FF=37000 µm2=124µm*300µm ConfigDoubleCol 42+4 add=46 2.7/ 4 Mhit/s columnFifo (depth= 6) columnFifoController clksync > 152FF @ 4 depth 7x12+1x6 46 46 quarterchipFifo&frameInserter Controller > clksync & enableclk sync register 90 clksync quarterChipMux 10 to 1 serialTimeMux 90 to 48 > clksync 48 46+4 add=50 quarter chip RO 0 quarter chip RO 3 quarter chip RO 2 quarter chip RO 1 data formatter & comma & frame inserter 48 min. 40 FIFOs 1 FIFO overflow bit, optional overflow count > > clksync & enableclk clksync & enableclk 8b10b encoder sync register 60 > > clkserial/2 serializer controller clkserial/2 clkmultiserial 27/ 40 Mhit/s parallelOut > 2 58 0 clkserial/2 serializer FIFO overflow status > 3 59 1 2.4/3.2 Gbits/s CML driver 4 x SLVS480/640 Mbit/s multiSerialPower clkmultiserial path d is doubled as to have one direct link from clkserial/2 to clkfiforead clkFIFOread 2 world clkserial/2 clksync global DACs clkmultiserial or clktest clkSerial=2.4/ 3.2 GHz c /2 /2 /5 /6 /2 /8 9+1x temp 0 1 band gap bandgap override 1 Modes: serialPLL2.4/serialPLL3.2/ext320/ext480/PLLoverride abc: /001010/110*010/111*011/101*010  8 modes = 3 bits clkInDigital=20/26.66/320/480/320MHz clkPLL=2.4/3.2/-/-/0.32GHz clksync=240(10)/ 320(10)/ 320*(0)/240*(2)/32(1) MHz clkFIFOread=40(60)/53(60)/27(12)/40(12)/5.3 MHz(60) clkmultiserial=480/640/320/480/64 MHz clkconfig=320/320/320/240/320 MHz ? if PLL runs on 480?? () =division factor, * can also be 0 or 1 to change clksync in TDC 0 PLL /6 1 0 /5 reset_corsecnt SLVS reset_global SLVS 0 0 PLL override e 2 (1 temp) 1 1 ext 1 a b c d config/statuschip 0 analogMonitorMux clkconfig test pulse b d f muxmode clkDigital=320/ 480 MHz > clkconfig SLVS320 MHz qchip clock divider & clk distribution SLVS≥320 Mbit/s 3 clkDll SLVS SLVS analog DC CMOS DC PLL SLVS 320/480MHz is located in synchronous logic; clk divider needs synchronous reset with respect to receiving clock domain (clkmultiserial) avg. nominal rate (750 MHz beam (104 Mhit/s per chip) / rate with 2.4 Gbiit/s serializer [Mhit/s]) = SEU protected

  3. 12000 µm Column 0 Corners: 125 µm Pixel = column * 45 + row Pixel group = column * 9+ group group 0 contains pixel 0 Pixel matrix: 13500 µm row 0 Band Gap 1100x400 Test pads 215x700 qchip 3 3000x500 qchip 2 3000x500 qchip 1 3000x500 qchip 0 3000x500 clk buffer & reset buffer & 20 clk dll buffers 12000 x 40 config 12000 x 300 Bgana 1400x300 Bgdig&temp 1500x300 PLL & 4 x Serializer & clk divider 8000 x 500 IO row 12000 x 400 (158 pads)

  4. 12000 µm Column 0 Corners: 125 µm row 0 Pixel = column * 45 + row Pixel group = column * 9+ group group 0 contains pixel 0 Pixel matrix: 13500 µm double column analog 0 double column analog 19 EoColumn bias 1800 µm TL rx: 70 µm double col. dig.0 double col. dig.19 hitArbiter & DLL, SM, fine registers & Coarse units, pixel group FIFOs, column FIFO 2477 µm Test pads 215x500=9 pads Quarter chip read-out 500 µm qchip 2 3000x500 qchip 1 3000x500 qchip 3 3000x500 qchip 0 3000x500 qchip & qconfig 3 3000x500 Clk_dll & reset_cc 72 µm clk buffer & reset buffer & 20 clk dll buffers 119000 x 72 Test pulse distributor 72 µm test pulse distributor 11900 x 72 config 11900 x 292 Configuration 292 µm BGana 1400x300 Bgdig&temp 1500x300 Serializer & PLL 500 µm PLL & 4 x Serializer & clk divider 8000 x 500 IO row 12000 x 400 (158 pads) IO row ~400 µm Total: > 19683 µm

  5. Top level schematic • is what you call left 0,2,4,6,8 • and right 1,3,5,7?

  6. TOP_KP_Serializer_4Cells • Only one pair of GND/VDD in symbol • Expecting: 4 pairs for each serializer + 1 pair for PLL • Where is sub connected to? • Question: which power supply is used for CML driver. • What are the drivers for the test pads? • Where is txResetA/B/C & testEnable connected to? • pll_dac_code = pll_select_i<3:0>? • pll_bandwidth_sel = pll_select_r<1:0>? • pll_test_enable = pll_pfd_test_en?

  7. Config • sdout = serial_conf_out? • missing: • enable_term • enable_term_serial_conf_in -> fixed or defaulted by register • slvs_out_cset_multi_serial<3:0> • slvs_out_cset_clkout<3:0> • slvs_out_cset_serial_conf_out<3:0> -> fixed or defaulted by register • pix_strobe stobe/b <19:0> is missing • is clk_mux_sel<0> = mux_sel_a 1 = b …

  8. config • Where is pll_test_a/b going? • where is reset_cc_cmd going? • is sdin_m_a/b/c serial_conf_in • where pll_instant_lock_m_a/b/c to? • where pll_test_mux_a/b<3:0> to? • e_co = err_fc?

  9. dll clock fanout • dll_clk_to_logic  tdc_clk_dll_tologic? • dll_clk tdc_clk_dll

  10. Colpair1 • no power connections • err_tc = ei?

  11. BandgapRHfinal • Analog band gap reference? • frcref connect to bandgapoverride? • to what kind of pad? • vhigh/vlow/lsub to where?

  12. tempinter • is this reference digital and temp out? • vhigh/vlow/lsub to where? • RTR = temp_adj_int • no override? for reference • to which kind of pad is temp going?

  13. Where to connect NX and SX in schematic of encounter blocks

  14. TDC • gnd power domains for tdc and dll are not separated, pins missing • why is not NX SX connection?

  15. serialPLL2_4lowClkSync = “001010 ext320highClkSync=“H100H0” H/L don’t care serialPLL2_4HighClkSync = “000010” ext480lowClkSync=“H110H1” H/L don’t care serialPLL3_2= “001000” ext480highClkSync=“H100H1” H/L don’t care clkmultiserial clkmultiserial clkmultiserial clkmultiserial clkmultiserial clkmultiserial clkmultiserial clkmultiserial path d is doubled as to have one direct link from clkserial/2 to clkfiforead path d is doubled as to have one direct link from clkserial/2 to clkfiforead path d is doubled as to have one direct link from clkserial/2 to clkfiforead path d is doubled as to have one direct link from clkserial/2 to clkfiforead path d is doubled as to have one direct link from clkserial/2 to clkfiforead path d is doubled as to have one direct link from clkserial/2 to clkfiforead path d is doubled as to have one direct link from clkserial/2 to clkfiforead path d is doubled as to have one direct link from clkserial/2 to clkfiforead clkFIFOread clkFIFOread clkFIFOread clkFIFOread clkFIFOread clkFIFOread clkFIFOread clkFIFOread clkserial/2 clkserial/2 clkserial/2 clkserial/2 clkserial/2 clkserial/2 clkserial/2 clkserial/2 clksync clksync clksync clksync clksync clksync clksync clksync clkSerial=2.4/ 3.2 GHz clkSerial=2.4/ 3.2 GHz clkSerial=2.4/ 3.2 GHz clkSerial=2.4/ 3.2 GHz clkSerial=2.4/ 3.2 GHz clkSerial=2.4/ 3.2 GHz clkSerial=2.4/ 3.2 GHz clkSerial=2.4/ 3.2 GHz c c c c c c c c /2 /2 /2 /2 /2 /2 /2 /2 ext320lowClkSync=“H110H0” H/L don’t care /5 /6 /5 /6 /2 /2 /2 /6 /6 /5 /5 /2 /6 /2 /6 /5 /5 /6 /5 /2 /6 /5 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /8 /8 /8 /8 /8 /8 /8 /8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Modes: serialPLL2.4/serialPLL3.2/ext320/ext480/PLLoverride abc: /001010/110*010/111*011/101*010  8 modes = 3 bits clkInDigital=20/26.66/320/480/320MHz clkPLL=2.4/3.2/-/-/0.32GHz clksync=240(10)/ 320(10)/ 320*(0)/240*(2)/32(1) MHz clkFIFOread=40(60)/53(60)/27(12)/40(12)/5.3 MHz(60) clkmultiserial=480/640/320/480/64 MHz clkconfig=320/320/320/240/320 MHz ? if PLL runs on 480?? () =division factor, * can also be 0 or 1 to change clksync in TDC 0 0 0 0 0 0 0 0 PLL PLL PLL PLL PLL PLL PLL PLL PLLoverride320=“101010” H/L don’t care /6 /6 /6 /6 /6 /6 /6 /6 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 /5 /5 /5 /5 /5 /5 /5 /5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL override PLL override PLL override PLL override PLL override PLL override PLL override PLL override e e e e e e e e 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ext ext ext ext ext ext ext ext 1 1 1 1 1 1 1 1 a a a a a a a a b b b b b b b b c c c c c c c c d d d d d d d d 0 0 0 0 0 0 0 0 clkconfig clkconfig clkconfig clkconfig clkconfig clkconfig clkconfig clkconfig b b b b b b b b d d d d d d d d f f f f f f f f muxmode muxmode muxmode muxmode muxmode muxmode muxmode muxmode clkDigital=320/480 MHz clkDigital=320/480 MHz clkDigital=320/480 MHz clkDigital=320/480 MHz clkDigital=320/480 MHz clkDigital=320/480 MHz clkDigital=320/480 MHz clkDigital=320/480 MHz qchip clock divider & clk distribution qchip clock divider & clk distribution qchip clock divider & clk distribution qchip clock divider & clk distribution qchip clock divider & clk distribution qchip clock divider & clk distribution qchip clock divider & clk distribution qchip clock divider & clk distribution 3 3 3 3 3 3 3 3 LVDS+2CMOS LVDS+2CMOS LVDS+2CMOS LVDS+2CMOS LVDS+2CMOS LVDS+2CMOS LVDS+2CMOS LVDS+2CMOS CMOS DC CMOS DC CMOS DC CMOS DC CMOS DC CMOS DC CMOS DC CMOS DC PLL PLL PLL PLL PLL PLL PLL PLL LVDS 320/480MHz LVDS 320/480MHz LVDS 320/480MHz LVDS 320/480MHz LVDS 320/480MHz LVDS 320/480MHz LVDS 320/480MHz LVDS 320/480MHz

  16. Qchip block diagram > > clksync clksync 10 x columnFifo 10 x serialReg 10 x 9 serial reg 10 *46 10 *columnFifo 90 10 *columnFifo > clksync & enableclk serial_time_x3mux 90 to 48 > clksync sync register qchip_controller_x3 pattern_control_x3 clksync > qchip_mux_x3 clksyncclksync& enableclk clkdll > 48 48 46+4 add=50 > clksync config_register_rw data_formatter_komma_frame_inserter_x3 > clksync 48 reset_synchronizer_x3_reset > > clksync & enableclk reset_synchronizer_x3_reset_coarse_counter 8b10b encoder enc8b10bx6_x3 clkdll sync register > clksync & enableclk register_qchip_word_x3 sync register enableclk > clksync clkfifo clock_enable_generator_x3 > clkmultiserial multi_serial_x3 60 enable > > clkserial/2 clkserial/2 clkconfig 27/ 40 Mhit/s > config_global 2 58 0 clkserial/2 serializer > 3 59 1 clkmultiserial or clktest 2.4/3.2 Gbits/s CML driver 4 x LVDS480/640 Mbit/s > clkmulitserial sync10b8b decoder_multi_serial clkword(recovered) 48 10 > clkword dec10b8b_x6 48 > clkword > serial_time_decoder clkword multi_serial_compare 48

  17. 2011.10.24 serialTime multiplexing SerialMux block diagram 9x10 7x12+1x6 12 serialTimeMux 12 to 1 > clksync 8x6=48 (116/6)*25ns=500 ns 6400 ns / 500 ns = 12.8

  18. dll statemachine 0 hit arbiter 0 & 1 clk_dll_sm reset_sync_s3 double column 0 > > > clk_dll_dc_0 to 19 reset_sync_s2 reset_cc_s2 clk_dll_qc 1 clk_sync_qc_1 clk_dll_qc 2 clk_sync_qc_2 clk_sync_qc_3 clk_dll_qc 3 clk_dll_qc 0 clk_sync_qc_0 qchip 0 qchip 3 qchip 1 qchip 2 clk_sync_qc_0 to 3 reset_sync_s1_ _qchip 0 to 3 1 1 1 1 4 20 4 4 20 reset_cc_s1_dc 0 to 19 & reset_cc_long_s1_qc 0 to 3 clk_dll_dc_0 to 19 clk_dll_config config 1 1 1 1 reset_synchronizer clk_dll reset_synchronizer & edge detector clk_dll clk_sync clk_sync clk_sync clk_sync clk_sync clk_dll clk_dll clk_dll > > > > > > > > > > clk_sync 0,1,2,3 reset_flip_flop reset_flip_flop reset_flip_flop 25 clk_dll_dc_0 to 19 & clk_dll_conig & clk_dll_qc 0 to 3 PLL & 4 x Serializer 1 1 1 clk_dll reset_sync reset_cc IO row

  19. Power domains

  20. min: clk_prop + hold; max: clk_prop+clk_cycle-setup cmd_reset_bandgap reset_bandgap_n from outside and analog blocks low active reset digital logic high active reset reset_synchronizer_sync D D D D D D Q Q Q Q Q Q _ _ _ _ _ _ Q Q Q Q Q Q voter clk_sync clk_sync clk_sync cmd_reset_sync cmd_config clk_config *) pin reset_all_n  reset_sync, reset_dll, reset_config, reset_bandgap_n *) cmd_reset_all  reset_sync, reset_dll, reset_config, reset_bandgap_n *) cmd_reset_sync  reset_sync *) cmd_reset_dll  reset_dll (to dll_state_machine) *) cmd_reset_config  reset_config *) cmd_reset_bandgap  reset_bandgap_n Reset scheme

  21. IOs • south end of chip: • 12 mm-2 corners*0.215 mm / 0.073 mm pitch = 158 • if possible only one rowoptional, two rows with power pins in the 2nd row (longer bond wires) • bond pads 200 µm long x ~ 70 µm wide • east and west end: • area accessible when sensor bonded: x mm  pads • area not accessible when sensor bonded: x mm  pads available for test pads in the EOC area

  22. I/O

  23. power densities examples: M1: Idc = 3.12*(W-0.06)=3.12*(1.4+0.7*(wd-1.4)-0.06) for 50 um -> 99 mA  1.98 mA/um M1: Irs = 7.52*(W-0.06)*sqrt(1.19+3.53/(W-0.06))= for 50 um 7.52*((1.4+0.7*(wd-1.4)-0.06)*sqrt(1.19+3.53/((1.4+0.7*(wd-1.4)-0.06))= 300 mA  6 mA/um M2,3: for 50 um -> Idc = 111 mA  2.22 mA/um MG,MQ,LM: for 50 um -> Idc = 191 mA  3.82 mA/um

  24. SIOVDD SIOVSS SIOVDD: M2: 23 um + MA: 17 um M2: Idc = 3.12*(W-0.06)=3.12*(1.4+0.7*(wd-1.4)-0.06) MA: Idc = 5.63*(W-0.27)=5.63*(1.4+0.7*(wd-1.4)-0.27) for 50 um -> 99 mA  1.98 mA/um Idc M2 = 51 uA + 68 uA = 119 uA SIOVDD,SIOVSS pads thin oxide: two big traces of M2 and MA, vertical & bars horizontal these bars even help for power density but abut to the next cell  We cannot have that as we have many different power domains. There are separation cells but they are 71 um wide and would waste space  Modification of the SIOVDD and SIOVSS is needed to avoid short circuits

  25. Data format • Nominal transmission: 2.4 Gbits/s, • High speed: 3.2 Gbits/s • All words: 48 bits (6 bytes) long • 8b10 encoded  bit stream 60 bits • data word • frame word • idle (komma) word: no hits available to transmit • sync word: after reset and after each force_sync command (can be sent repetitive) • Header contains frame counter every 2048 clock_dell cycles (at 320 MHz ~ every 6.4 µs) • Data contains dynamic range up to 6.4 µs + 1 overroll counter bit

  26. Data format-hit word normal mode (48 bit) • ------------------------------------------------------------------ • --qchip_word -> data_out • ------------------------------------------------------------------ • --(47) Status/data selector 1 bit • --(46..40) Address 7 bit (90 pixel groups) • --(39..35) Address-hit arbiter 5 bit • --(34..30) Address pileup 5 bit • --(29) Leading coarse time selector 1 bit • --(28..17) Leading coarse time 12 bit 1bit rollover indicator+2048(11bit)*3.125 ns=6.4 µs • --(16..12) Leading fine time 5 bit 98 ps -> 3.125 ns • --(11) Trailing coarse time selector 1 bit • --(10..5) Trailing coarse time 6 bit 64*3.125 ns = 200 ns • --(4..0) Trailing fine time 5 bit 98 ps -> 3.125 ns • ___________________________________________________________ • --Total 48 bit

  27. (45..39) Address 7 bit (90 pixel groups) • 10 column each 9 pixels groups to be addressed: • Column 0: pixel group 0,1,2,3,…,7,8 • Column 1: pixel group 9,10,11,12,13..17 • Column 2: pixel group 18,19,20,21,..26 • …. • pixels in pixel group are one hot encoded • example pixel 2: “00010”

  28. Frame word (ex frame 0) • word_frame0(27 downto 0) <= frame_counter; • word_frame0(36 downto 28) <= hit_counter; • word_frame0(42 downto 37) <= qchip_collision_count; • word_frame0(46 downto 43) <= “0000” not used; • word_frame0(47) <= '1'; --format bit • ------------------------------------------------------------------ • --(47) status bit 1 bit • --(46..43) not used = ‘0’ 4 bit • --(42..37) # of collisions in previous frame 6 bits • -- 2**6=64, 3.3 MHz*10*6.4us=211hits --> count to 64 allows 1/3 of hits to collide • --(36..28) # of hits in previous frame 9 bits • -- hits per qchip and frame= 130 Mhits/s/4*6.4us=208-> • -- max hits in frame: worst case: clk_dll = 240 MHz clk_sync = 320MHz clk serial 3200 MHz-> number of -> 2048 / 240 MHz = 8.53 us frame length -> transmission cycles in one frame : 8.53 us *(3200MHz / 60)= 455 -> 9 bit • --(27..0) framecounter 28 bit • -- 2**28*6.4us=1718s • ______________________________________word_frame1 suppressed

  29. sync link word (48 bit) sent after reset for 1024 clk cyclesSUPPRESSED • 6 * Komma K28.5___________________________________________________________________________________ • Total 6 * 48 bit

  30. sync slot word (48 bit) sent after reset or reset_cmd for 2^16 = 65536 times -> @ 320 MHz  3.125 ns * 6 * 65536 = 1.23 milliseconds • 5 * Komma K28.5+ 1 K27.7 + K27.7 is sent after 5 Kommas___________________________________________________________________________________ • Total 6 * 48 bit

  31. idle word (48 bit) • 5 * Komma K28.5+ 1 K27.7 + K27.7 is sent after 5 Kommas___________________________________________________________________________________ • Total 6 * 48 bit

  32. Do we need these values in frame • Seu_counter • FIFO_overflow_counter • Error_info • Status_info • Checksum

  33. Configuration: qChip • ----------------------------------------------------------------------- • --configuration register • ----------------------------------------------------------------------- • send_k_sync_requ <= configuration_data_int_in(0); • send_k_word_requ <= configuration_data_int_in(1); • k_word_type <= configuration_data_int_in(5 downto 2); • enable_serial_time_int <= configuration_data_int_in(6); • enable_test_pattern_int <= configuration_data_int_in(7); • new_data_testpattern <= configuration_data_int_in(8); --01 transisition counts • -- this bit acts as write command for the data_testpattern fifo, each 01 transition is used as write cmd • data_testpattern <= configuration_data_int_in(9+data_test_pattern_width-1 downto 9); • -- 54 bit: data_testpattern -> write data into cell 54 of data_testpattern -- 48 data + 6 k indicator • --> subsequent writing moves write pointer of FIFO so that all 8 FIFO cells can be • --> written • --> when test pattern FIFO is used, all 8 FIFO cells are read and pushed into • --> the data stream, thus the data stream consists of a multiple of 8 data words.

  34. Configuration: TDC

  35. Configuration: DLL

  36. Configuration: EOC bias

  37. Configuration: pixel

  38. Configuration: config

  39. G. Aglieri

  40. G. Aglieri

  41. G. Aglieri

  42. Status • schematic or hdl • simulation pre-layout / pre-synthesis • layout & extraction • simulation post-layout / parasitics back annotated • DRC & LVS • schematic integrated in top • layout integrated in top • simulation integrated in top • SEU simulation

  43. Clock tree&divider 60bit 5pads

  44. Implementation data transmission 60b • Using GBT running at 20 MHz, but modifying data shift length to 60 • Problem: GBT has 3 parallel multiplexed shift registers, 60/3=20GBT can to be modified to 2 SR each 30 bits, first clock divider from 3 to 2additional high speed dividers • 20 MHz in  2.4 Gbit/s  40 Mwords/s (+21% (132 Mhits/s); + 54% (104 Mhits/s) • 2400 / 320 = 7.5 !  2400/8 = 300 MHz • Programmable divider: 10 (240) / 5! (480) / 60 (40) for synchronous read logic • Programmable divider: 8 (300), 6(400) for FIFO write and state machines • Synchronous parallel read-FIFO frequency: • serialFrequ * n / 50 [MHz] = 48 (1)/96(2)/144(3)/192/240(10)/288/336/384/432/480 (5!) 20 MHz 2.4 GHz PLL • Fast counter: • /2 = 1.2 GHz serial mux & shift • /5 /2 = 240 MHz fifo read • /5/2 = 240; /2 /4 = 300 MHz; /3 /2 = 400 MHzstatemachines, all FIFOs&chipFIFOwrite 1.2 GHz serial mux & shift 40 MHz parallel_load (/60) Clock divider 2.4 GHz 40 MHz (60) / 240 MHz (10) / 480 MHz (5!) Fifo read 240 MHz (10) / 300 MHz (8) / 400 (6) Fifo write

  45. Implementation data transmission; 60bit/5IO • Multi Serial60bit: • 60 bits (8b10); 5 I/O pairs • FIFO read-frequency for 50% contingency on 132 Mhits/s  50 MHz / quarter chip * 60 bit /5 pairs (10 bits serializer)  3000 /5 = 600 MHz per LVDS pair • Input frequency comes from PLL or from outside, either 2.4 Gbit/s on pad or 480 MHz for all pads & synchronous logic • if synchronous logic works with 480 MHz only  480 MHz * 5 = 2400 Mbit/s  / 60  40 Mhits/s  (21 % (132 Mhits/s) +54 % (104 Mhit/s)) • Worst case • synchronous logic works with 320 MHz only  320 MHz * 5 = 1600 Mbit/s  / 60  26.7 Mhits/s  (-19 % (132 Mhits/s) +3 % (104 Mhit/s)) • synchronous logic works with 240 MHz only  240MHz * 5 = 1200 Mbit/s  / 60  20 Mhits/s  (-39 % (132 Mhits/s) -23 % (104 Mhit/s))

  46. Implementation data transmission 60b • Using GBT running at 26.66 MHz • 26.66 MHz in  3.2 Gbit/s  53 Mwords/s (+61 % (132 Mhits/s); + 105 % (104 Mhits/s) • 3200 / 320 = 10  • Programmable divider: 10 (320) 26.66 MHz 3.2 GHz PLL 3.2 GHz 53MHz parallel_load (/60) Clock divider 3.2 GHz 53 MHz (60) / 320 MHz (10) / 640MHz (5!) Fifo read 320MHz (10) / 400 MHz (8) / 533.33 (6) Fifo write

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