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Software Defined Radio

Software Defined Radio. 4. Data Conversion in Software Defined Radios 4.1 The importance of data converters in software defined radios 4.2 converter architectures 4.3 converter performance impact on SDR 4.4 conclusions and future trends Kyung-Ho Chung.

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Software Defined Radio

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  1. Software Defined Radio 4. Data Conversion in Software Defined Radios 4.1 The importance of data converters in software defined radios 4.2 converter architectures 4.3 converter performance impact on SDR 4.4 conclusions and future trends Kyung-Ho Chung khjung21@hanmail.net

  2. Contents 4.1 The Importance of data converters in software defined radios 4.1.1 ADCs for SDR Base stations 4.1.2 ADCs for SDR Handsets 4.1.3 DACs for SDR Applications 4.2 Converter Architectures 4.2.1 Flash Converters 4.2.2 Multistage Converters 4.2.3 Sigma-Delta Converters 4.2.4 Digital-to- Analog Converters 4.3 Converter Performance Impact on SDR 4.3.1 Noise Sources-Impact on SDR Sensitivity - Quantization Noise - Differential Nonlinearity - Thermal Noise, - Jitter

  3. Contents 4.3.2 SNR of the Data Converter - Noise Figure - Effective Number of Bits (ENOB) 4.3.3 Spurious Impact on Performance - Integral Nonlinearities - Slew Rate Limitation - Aperture Error - Harmonics - Intermodulation Distortion - Carrier to Interference Ratio - Dither - Spread Spurious 4.4 Conclusions and Future Trends

  4. 4.1 The Importance of Data Converters in SDR • The use of converters in SDR depends upon the overall radio architecture. Table 4.1 Summary of sampling strategies for SDR receivers

  5. 4.1.1 ADCs for SDR Base Stations (1/3) • The realities of the wireless industry have moved the idea of SDR into new applications. • Consider to economics with direct implication on size, power consumption and complexity. • SDR concepts are finding initial acceptance and usage primarily in base station applications. • In this case, ADC is critical for the system operation.

  6. 4.1.1 ADCs for SDR Base Stations (2/3) • Base station architectures may take into consideration either quadrature baseband sampling or IF sampling. • Base station designs rely on best available converters in the class with highest resolution and widest operating bandwidth. • Available state-of-the-art ADCs for wireless applications are 14-bit resolution devices operating in excess of 100 MHz, But there is an increased demand from base station manufacturers for 16-bits ADCs operating in excess of 120 MHz.

  7. 4.1.1 ADCs for SDR Base Stations (3/3) • Converters with higher bit resolutions can process higher dynamic ranges. • Unlike single carrier IF sampling solutions, it is much more difficult to place the spurious content out of the band of interest in a multicarrier solution, because of the large number of carriers. • The aliased spurs of one carrier are likely to fold back on the same carrier or another carrier. • This occurrence places a greater requirement on the SFDR of the ADC than a single carrier does. • Thus, the SFDR is usually the limiting factor for a wideband system.

  8. 4.1.2 ADCs for SDR Handsets • Considering the strict power limitation of handsets, different approaches have been applied to the design of ADCs for such usage: • bandpass sampling for single standard terminals • reconfigurable converters reusing hardware blocks for multimode terminals. • Introduction of the 3G wireless standards is increasing the importance of multimode terminals. • The focus of design will be on multimode radios with some sort of reconfigurable converter that can provide performance/complexity trade-off.

  9. 4.1.3 DACs for SDR Applications • High performance digital-to-analog converters(DACs) are specifically used in the transmit(Tx) signal path to reconstruct on or more carriers that have been digitally modulated. • More of the signal processing in these new generations of communication equipment is being performed in the digital domain for multiple reasons. • Higher capacity. • Improved quality. • Lower power. • Software programmable. • Many of these DSP functions are being integrated with the DAC itself to enhance its performance and to enable new transmitter architectures.

  10. 4.2 Converter Architectures • new architecture → a trend toward higher integration, lower power, increased performance • It is essential to understand each of these architectures so that the best converter can be selected for given communications system. • 4.2.1 Flash Converters • One of the first data converter Architectures • A flash or parallel converter consists of 2N-1 comparators, where N is the number of digital output codes.

  11. 4.2.1 Flash Converters • Many benefits. 1) Extremely fast conversion times. 2) For low resolution applications, premium performance can be obtained at a minimum cost.→ attractive flash converters for applications where dynamic range requirements are minimal. • Biggest drawback to this Architectures 1) As the number of bits increases, the size of the chip, costs, and complexity increase at an exponential rate of 2N. 2) In practice, there are very few flash ADCs larger than 10 bits because of the relatively large die sizes. 3) Beyond this point (e.g. big, complex), thus adversely impacting on cost

  12. The overcome of the complexity problem, 1) different architectures have been developed which use fewer comparators such as in folded flash or pipelined architectures. • 2) In addition, as the number of comparators increases, the reference voltages get smaller. • ⇒ as the the reference voltage is reduced, the offset voltage of comparator is approached. • ⇒ once this happens, the linearity and overall performance of the converter is compromised • ⇒ as more comparators are connected to the analog input, the input capacitance increases. With the increased capacitance, the effective signal bandwidth is reduced, defeating the high speed benefit of the parallel converter.

  13. several anomalies associated with the flash architecture • - Basic linearity • (the differential nonlinearity (DNL), the integral nonlinearity (INL)) • 1) the overall linearity of a flash converter • - by the linearity of the resistive ladder • 2) because of input leakage current of comparators, • these additional currents in the ladder can affect both the DNL • and INL • 3) DNL, INL : performance of a receiver

  14. 4.2.2 Multistage Converters • Architecture used in high speed, high resolution ADC 1) The Key advantage: Its Scalability 2) The end resolution ⇒ by increasing and decreasing the bit precision of each stage (trade-offs) 3) This architecture : up to 16 bits and beyond 4) The ability to construct high resolution converter : in many SDR applications • When comparing a multistage ADC with a single stage flash or pipeline ADC, many advantages exist. 1) over CMOS pipeline architectures: very high precision, (be important in many communications applications)

  15. 2) over single stage flash converters: much less die area. (because of far fewer comparator), ⇒ improved yield, lower power, lower overall cost. • Although a multistage ADC has many advantages, It does have some very challenging design requirements. ⇒strict requirements on the first conversion stage DAC(DAC1). Because this DAC represents the reference for the entire ADC, it must have a resolution greater than the overall number of bits for the entire ADC.

  16. 4.2.3 Sigma-Delta Converters • A highly innovative and relatively new idea in the ADC technology 1) In wireless applications, ∑Δ ADC can offer integration. 2)∑Δ ADC consists of an analog filter, a quantizer (comparator), a decimation digital filter circuit, and a DAC. 3)∑Δ modulators work by sampling faster than the Nyquist criterion and making the power spectral density of the noise nearly zero in a narrow band of signal frequencies. (quantization noise shaping) 4) Oversampling pushes out the noise. 5) Decimation filters 6) Characterization by Sigma-delta converters SNR 7) Regarding their front end analog signal frequency: lowpass, bandpass modulators

  17. 8) The simplest form of an ∑Δ ADC : first-order loop filtering, single bit comparator. • In a second-order ∑Δ modulator, doubling sampling reduce the noise power and increases resolution 1) To further increase the bandpass / lowpass signal resolution: high order modulators ← To improve the noise shaping 2) An L th order loop filter: improves the signal ← by improving the high-pass filtering of quantization noise 3) Stability: high order loop filters (L>2) 4) Stable operation: for limited input power 5) SNR increases at L + 0.5 bits/octave. 6) L>2 : worrisome problem

  18. The key factor in the development: low cost, good linearity • The advantage: not require high precision and accurately trimmed analog components 1) Sigma delta ADCs: low cost CMOS circuitry 2) Due to their Noise shaping behavior: an attractive approach • Oversampling( two advantage): 1) first- the specification of the analog anti-alias filter is reduced. 2) second- the n-bit resolution can be increased to n+1 bit • Trade off: digital processing requirement( lowpass filtering: comb filter and FIR filter) against a reduction in the provision of accurately trimmed analog component and complexity • Well suited for use in SDR ( for direct or for bandpass sampling) • By employing a bandpass loop filter and feedback : bandpass modulator⇒ quantization noise ↓

  19. 4.2.4 Digital-to-Analog Converters • Most high speed CMOS DACs: an architecture based on current segmentation and edge-triggered input data latches • Figure 4.4: a typical segmentation architecture

  20. 1) The upper 4 or 5 binary weigthed bits (MSBs): thermometer decoded, identical current sources, switches 2) To optimize DC linearity performance: each of these identical current source → unit current source 3) The binary-weighted bits (LSBs): current segmentation (unit current source) 4) The remaining LSBs: The binary-weighted current source * The weighted current source can be switched output nodes. * The differential switches (figure 4.5)

  21. These current source: an internal control amplifier • An external resistor • The sum of all the currents: the DAC full scale current, IOUTFS(20dB range: 2~20mA) • The architectural approach : various difference in the actual implementation ( affecting a high speed DAC performance, system requirments) ▪ For example, DC linearity performance ⇒ use some form of factory calibration technique • The objective (differential switches) ▪ to achieve fast, symmetrical switching characteristics with minimum time skew between the differential current switches

  22. 4.3 Converter Performance Impact on SDR • The major behavioral characteristics of data converter: their impact on SDR performance, primarily in terms of noise and spurious generation 4.3.1 Noise sources - Impact on SDR sensitivity • The Noise within data converter : not always thermal in nature (a significant portion of the overall noise) ▪ Noise from quantization (digitization) ▪ DNL errors (nonideal quantization) ▪ clock jitter ▪ numerous other sources

  23. 4.3.1.1 Quantization Noise • Quantization : the digitization of the analog input, 2N ( N:the number of physical bits that converter represents) • For a flash ADC ▪ the signal to quantization noise: • For sigma-delta converter (due to noise shaping) 4.3.1.2 Differential Nonlinearity (DNL) • DNL: step-by-step variation in quantization or converter step size • Associated the static or DC performance of converter • Affect of The noise performance

  24. Failure to indicate total noise (the absence of thermal noise) • Signal level (small ralative to the full scale of the converter) ⇒ DNL errors (large with respect to the input signal) • Since most receivers are AC coupled, small signal performance centers on the midscale of the converter ⇒ DNL at the midpoint of the converter: Important • Codes that deviate from normal size ⇒1. increase overall noise, reduce the sensitivity of the receiver. 2. DNL errors at midscale can cause apparent gain errors

  25. Figure 4.6

  26. 4.3.1.3 Thermal noise • Another source of noise • Related to the design and process • The equation • Process→ limited by the device physics (* parasitic resistance of Transistor) • The overall thermal noise performance: the base to emitter (rb) resistance of these Transistor

  27. 4.3.1.4 Jitter • 1) ADC aperture jitter: The final contributor to dynamic specification that is vital to radio performance 2) Aperture jitter: the sample to sample variations in the clock source 3) Clock path jitter: internal and external jitter source anywhere between the clock source and the actual sampling mechanism • The overall effect of a poor jitter specification: an increase in the converter noise level • ‘Aperture jitter’ = ‘Aperture uncertainty’ • In sinewave, the maximum slew rate (the derivative) at the zero crossing * How fast the signal is slewing

  28. In a sampling system, If the sample clock has the aperture uncertainty, an error voltage is generated 1) the error voltage: volts rms (unit) 2) this equation show: analog input frequency ↑, the rms error voltage ↑ ∝ aperture uncertainty • In IF sampling converter, clock purity is of extreme importance • 1) As aperture uncertainty is wideband noise on the clock, it shows up as wideband noise in sampled spectrum as well 2) This wideband noise degrades the noise floor performance of ADC 3) The theoretical SNR for an ADC as limited by aperture uncertainty

  29. 4.3.2 SNR of the data converter • When computing the sensitivity of receiver : the most useful computational specification 1) When considering overall converter performance: a more generalized equation (the thermal noise effect) 2) the noise analysis ( FFT analysis) → noise energy: the summation of all the noise energy in the spectrum including any spurious signals and harmonics 3) Determined for the Operating condition of the receiver

  30. 4.3.2.1 noise figure • Noise figure calculation requirement: the full scale input voltage, termination impedance, sample rate, and SNR • The first step ⇒ the equivalent input power range (by computing the rms input voltage range)

  31. 4.3.2.2 Effective Number of Bits (ENOB) • To express the relative performance of a data converter not by SNR, but by the effective number of bits 1) Accounts for all errors within the ADC: thermal, equantization, aperture jitter, and DNL 2) Useful in comparing various data converters

  32. 4.3.3 Spurious Impact on performance • Limit: noise∝ sensitivity, spurious signal (generated within the receiver) ∝ performance 1) Internally generated spurious → as small as possible 2) Spurious source: numerous, very complex to predict (in the case of higher order mixer terms) 3) For ADCs, the linearity of the system • 1) Useful in predicting spurious performance of a data converters 2) Useful for determining both single and multi sinusoidal inputs ← harmonic, intermodulation performance 3) Many Characteristics : Frequency dependant

  33. 4.3.3.1 Integral nonlinearities (INL) • The static transfer function error of an ADC • The deviation of the transfer function from a best fit line • Integrating the DNL for each and every code of the transfer function can represent INL 4.3.3.2 Slew rate Limitation • The other main contributor to transfer function errors • Example: converter that is designed on a bipolar process and employs a track-and-hold • These linearity errors: frequency dependant, difficult to predict ▪ related to device physics of elements used within the design

  34. 4.3.3.3 Aperture Error • Another error that causes frequency dependant distortion • Different from aperture jitter • Involve the sampling process • Relate to how the sample is made • Figure 4.8 insert

  35. 4.3.3.4 Harmonics • Provide Measurements of various dynamic tests - harmonic distortion (dBc or dBFS (dB full scale)) • Useful in determining the suitability and anticipated performance of a data converter • High performance data converter will specify harmonic performance for a variety of operating condition to allow for adequate validation of the suitability of a device for a given application

  36. Figure 4.9

  37. 4.3.3.4.1 Intermodulation Distortion • 1) For example, from the nonlinear term K2 , the new terms f1– f2 and f1 + f2 are generated. 2) from the nonlinear term K3 , the new terms 2f1– f2 and 2f2– f1 are generated - in band, near the signals of interest • Issue : Intermodulation between the individual component • Intefered with desired signal ← These spurious term • 1) For linearity devices, the third-order intercept point IP3 (the normal specification) 2) most data converters have exceptional third-order distortion terms. 3) in effect, the spurious products within a well designed ADC: not by intermodulation but by DNL anomalies

  38. figure 4.10

  39. the resulting third order products 4.3.3.5 Carrier to Interference Ratio • The specification that relates to SFDR • IF an interferer is sufficiently large ⇒ spur (potentially blocking the desired call)

  40. 4.3.3.6 Dither • The dither: pseudo random noise • One technique that is used to improve SFDR • In a multistage ADC, to improve the DNL errors

  41. 4.3.3.7 Spread Spurious • In emerging wireless standards ⇒ data bandwidth ↑ ⇒ wider frequency ⇒the fundamental energy is spread • Harmonic energy ⇒ smear : noise floor ⇒ degrading the overall sensitivity ⇒ consider: when selecting an ADC for a wideband application • At sufficiently wide bandwidths - ★Numbers such as signal-to noise and distortion (SINAD) • In sensitivity calculations : SNR, SINAD

  42. 4.3.4 Digital to Analog Converter specification • Because of Static and dynamic nonlinearities, in frequency domain themselves ↑ 1) Static nonlinearity errors (INL and DNL performance) : determine⇒ the ultimate performance capabilities of the converter (most evident at lower input signal frequency and level) 2) Dynamic nonlinearity: performance degradation at higher input frequency and signal level 3) SFDR (the most often quoted specification): the difference between fundamental and the largest spurious signal 4) The noise performance of a DAC ⇒ determine : DAC’s suitability the carrier to noise ratio ⇒ affect : the bit error rate (BER)

  43. Predict: easily ⇒ The effects of quantization on a DAC’s noise performance difficult ⇒ additive noise effect (DNL), digital feed through, jitter • ACP (adjacent channel power) performance: 1) the ratio of reconstructed signal power to to the power measured in an adjacent channel 2) an application specific specification, 3) in determining a DAC’s suitability for certain application 4) limited by its noise floor and distortion performance (reconstructing the modulated carrier): the ACP performance of a DAC

  44. 4.4 Conclusions and Future Trends • Data converter : an important role in SDR Develop : data converter → focus : SNR, SFDR, bandwidth, sample rate (trade-offs) ⇒ determine: the capabilities of future SDRs • 1) The design of the ADC utilized in the receiver 2) Trade-offs (for a high speed, high resolution ADC): bandwidth, noise performance ( better spurious performance → wider input bandwidth → more noise for ADC → extra noise → degrade the SNR performance • Consideration : System level 1) a fixed input range → additional range → gain control, SNR 2) system noise requirement (related SFDR) → given the C/I requirement, a harmonic → be set to conversion gain 3) conversely, excess conversion gain → dynamic range (limit) → in order to optimize the signal range → gain, noise figure(minimize)

  45. 4.4 Conclusions and Future Trends • The major mechanism influencing Data converter : aperture jitter • The key challenge (for the future) : 1) aperture jitter (reduce) 2) maximum sampling frequency (increase) while maintaining low power consumption • One new approach for SDR : superconductor ultra fast IC logic (Rapid Single Flux Quantum) • New approaches to DAC : digital to RF architecture based on sigma-delta modulation • sigma-deltaconverter : the Power restrictions, wireless handset, possibility of integration → reconfigurable converter

  46. Data conversion : a critical aspect of commercial wireless product • Investment⇒ as mobile phones transition to higher data rate multimedia personal communications device

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