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55:035 Computer Architecture and Organization

55:035 Computer Architecture and Organization. Lecture 6. Outline. Memory Arrays and Hierarchy SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Serial Access Memories Flash DRAM. Memory Arrays. Levels of the Memory Hierarchy. CPU.

cameron-nicholson
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55:035 Computer Architecture and Organization

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  1. 55:035Computer Architecture and Organization Lecture 6

  2. Outline • Memory Arrays and Hierarchy • SRAM Architecture • SRAM Cell • Decoders • Column Circuitry • Multiple Ports • Serial Access Memories • Flash • DRAM 55:035 Computer Architecture and Organization

  3. Memory Arrays 55:035 Computer Architecture and Organization

  4. Levels of the Memory Hierarchy CPU Part of The On-chip CPU Datapath ISA 16-128 Registers Farther away from the CPU: Lower Cost/Bit Higher Capacity Increased Access Time/Latency Lower Throughput/ Bandwidth Registers One or more levels (Static RAM): Level 1: On-chip 16-64K Level 2: On-chip 256K-2M Level 3: On or Off-chip 1M-16M Cache Level(s) Dynamic RAM (DRAM) 256M-16G Main Memory Interface: SCSI, RAID, IDE, 1394 80G-300G Magnetic Disc Optical Disk or Magnetic Tape 55:035 Computer Architecture and Organization

  5. Memory Hierarchy Comparisons Capacity Access Time Cost faster Staging Xfer Unit CPU Registers 100s Bytes <10s ns Registers prog./compiler 1-8 bytes Instr. Operands Cache K Bytes 10-100 ns 1-0.1 cents/bit Cache cache cntl 8-128 bytes Blocks Main Memory M Bytes 200ns- 500ns $.0001-.00001 cents /bit Memory OS 4K-16K bytes Pages Disk G Bytes, 10 ms (10,000,000 ns) 10 - 10 cents/bit Disk -5 -6 user/operator Mbytes Files Larger Tape infinite sec-min 10 Tape -8 55:035 Computer Architecture and Organization

  6. Connecting Memory Memory Processor k -bit address bus MAR n -bit data bus k Up to 2 addressable MDR locations Word length = n bits Control lines R / W ( , MFC, etc.) 55:035 Computer Architecture and Organization

  7. Array Architecture • 2nwords of 2mbits each • If n >> m, fold by 2k into fewer rows of more columns • Good regularity – easy to design • Very high density if good cells are used 55:035 Computer Architecture and Organization

  8. 6T SRAM Cell • Cell size accounts for most of array size • Reduce cell size at expense of complexity • 6T SRAM Cell • Used in most commercial chips • Data stored in cross-coupled inverters • Read: • Precharge bit, bit_b • Raise wordline • Write: • Drive data onto bit, bit_b • Raise wordline 55:035 Computer Architecture and Organization

  9. SRAM Read • Precharge both bitlines high • Then turn on wordline • One of the two bitlines will be pulled down by the cell • Ex: A = 0, A_b = 1 • bit discharges, bit_b stays high 55:035 Computer Architecture and Organization

  10. SRAM Write • Drive one bitline high, the other low • Then turn on wordline • Bitlines overpower cell with new value • Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 • Force A_b low 55:035 Computer Architecture and Organization

  11. SRAM Column Example Read Write 55:035 Computer Architecture and Organization

  12. Decoders • n:2n decoder consists of 2n n-input AND gates • One needed for each row of memory • Build AND from NAND or NOR gates 55:035 Computer Architecture and Organization

  13. Large Decoders • For n > 4, NAND gates become slow • Break large gates into multiple smaller gates 55:035 Computer Architecture and Organization

  14. Column Circuitry • Some circuitry is required for each column • Bitline conditioning • Sense amplifiers • Column multiplexing 55:035 Computer Architecture and Organization

  15. Bitline Conditioning • Precharge bitlines high before reads • Equalize bitlines to minimize voltage difference when using sense amplifiers 55:035 Computer Architecture and Organization

  16. Differential Pair Amp • Differential pair requires no clock • But always dissipates static power 55:035 Computer Architecture and Organization

  17. Column Multiplexing • Recall that array may be folded for good aspect ratio • Ex: 2 kword x 16 folded into 256 rows x 128 columns • Must select 16 output bits from the 128 columns • Requires 16 8:1 column multiplexers 55:035 Computer Architecture and Organization

  18. Multiple Ports • We have considered single-ported SRAM • One read or one write on each cycle • Multiported SRAM are needed for register files • Examples: • Multicycle MIPS must read two sources or write a result on some cycles • Pipelined MIPS must read two sources and write a third result each cycle • Superscalar MIPS must read and write many sources and results each cycle 55:035 Computer Architecture and Organization

  19. Dual-Ported SRAM • Simple dual-ported SRAM • Two independent single-ended reads • Or one differential write • Do two reads and one write by time multiplexing • Read during ph1, write during ph2 55:035 Computer Architecture and Organization

  20. Multi-Ported SRAM • Adding more access transistors hurts read stability • Multiported SRAM isolates reads from state node • Single-ended design minimizes number of bitlines 55:035 Computer Architecture and Organization

  21. Serial Access Memories • Serial access memories do not use an address • Shift Registers • Tapped Delay Lines • Serial In Parallel Out (SIPO) • Parallel In Serial Out (PISO) • Queues (FIFO, LIFO) 55:035 Computer Architecture and Organization

  22. Shift Register • Shift registers store and delay data • Simple design: cascade of registers • Watch your hold times! 55:035 Computer Architecture and Organization

  23. Denser Shift Registers • Flip-flops aren’t very area-efficient • For large shift registers, keep data in SRAM instead • Move read/write pointers to RAM rather than data • Initialize read address to first entry, write to last • Increment address on each cycle 55:035 Computer Architecture and Organization

  24. Tapped Delay Line • A tapped delay line is a shift register with a programmable number of stages • Set number of stages with delay controls to mux • Ex: 0 – 63 stages of delay 55:035 Computer Architecture and Organization

  25. Serial In Parallel Out • 1-bit shift register reads in serial data • After N steps, presents N-bit parallel output 55:035 Computer Architecture and Organization

  26. Parallel In Serial Out • Load all N bits in parallel when shift = 0 • Then shift one bit out per cycle 55:035 Computer Architecture and Organization

  27. Queues • Queues allow data to be read and written at different rates. • Read and write each use their own clock, data • Queue indicates whether it is full or empty • Build with SRAM and read/write counters (pointers) 55:035 Computer Architecture and Organization

  28. FIFO, LIFO Queues • First In First Out (FIFO) • Initialize read and write pointers to first element • Queue is EMPTY • On write, increment write pointer • If write almost catches read, Queue is FULL • On read, increment read pointer • Last In First Out (LIFO) • Also called a stack • Use a single stack pointer for read and write 55:035 Computer Architecture and Organization

  29. DRAM Timing SRAM Timing Self-timed Multiplexed Adressing Memory Timing: Approaches 55:035 Computer Architecture and Organization

  30. D G S Non-Volatile Memories • Floating-gate transistor Floating gate Gate Source Drain t ox t ox + +_ n n p Substrate Schematic symbol Device cross-section 55:035 Computer Architecture and Organization

  31. NOR Flash Operations ―Erase 55:035 Computer Architecture and Organization

  32. NOR Flash Operations ―Program 55:035 Computer Architecture and Organization

  33. NOR Flash Operations ―Read 55:035 Computer Architecture and Organization

  34. NAND Flash Memory Word line(poly) Unit Cell Source line (Diff. Layer) 55:035 Computer Architecture and Organization Courtesy Toshiba

  35. Read-Write Memories (RAM) • Static (SRAM) • Data stored as long as supply is applied • Large (6 transistors/cell) • Fast • Differential • Dynamic (DRAM) • Periodic refresh required • Small (1-3 transistors/cell) • Slower • Single Ended 55:035 Computer Architecture and Organization

  36. 1-Transistor DRAM Cell • Write: Cs is charged or discharged by asserting WL and BL • Read: Charge redistribution takes place between bit line and storage capacitance • Voltage swing is small; typically around 250 mV 55:035 Computer Architecture and Organization

  37. DRAM Cell Observations • 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. • DRAM memory cells are single ended in contrast to SRAM cells. • The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. • 1T cell requires presence of an extra capacitance that must be explicitly included in the design. • When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD 55:035 Computer Architecture and Organization

  38. V V (1) BL V PRE Δ V (1) V (0) t Sense amp activated Word line activated Sense Amp Operation 55:035 Computer Architecture and Organization

  39. DRAM Timing 55:035 Computer Architecture and Organization

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