Steve miller chief engineer
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Requirements for Scalable Application Specific Processing in Commercial HPEC. Steve Miller Chief Engineer. The 3 Single-Paradigm Architectures. App-Specific Graphics - GPU Signals - DSP Prog’ble - FPGA Other ASICs. Scalar Intel Itanium SGI MIPS IBM Power Sun SPARC HP PA. Vector

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Steve Miller Chief Engineer

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Steve miller chief engineer

Requirements for Scalable Application Specific Processing

in Commercial HPEC

Steve Miller

Chief Engineer


The 3 single paradigm architectures

The 3 Single-Paradigm Architectures

App-Specific

Graphics - GPU

Signals - DSP

Prog’ble - FPGA

Other ASICs

Scalar

Intel Itanium

SGI MIPS

IBM Power

Sun SPARC

HP PA

Vector

Cray X1

NEC SX


Paradigms to applications

Paradigms to Applications

Application-specific

Application-specific

Scalar

Vector

Low Compute high

Intensity

Low Data locality High


Architectural challenges

Architectural Challenges

  • Hardware

    • Bandwidth to/from System

    • Scalability

  • Software

    • Compliers/Languages

    • Debuggers

    • APIs


Multi paradigm computing ultraviolet

Multi-Paradigm Computing UltraViolet

Scalar

Scalar

Vector

IO

IO

Vector

Compute

FPGA

Graphics

DSP

Reconfigurable

Terascale to Petascale Data Set :

Bring Function to Data

Scalable Shared Memory

. Globally addressable

. Thousands of ports

. Flat & high bandwidth

. Flexible & configurable


Software

Software

  • Provide for HDL modules

    Integrated environment with debugger

    Highest performance

  • Leverage 3rd Party Std Language Tools

    Celoxia, Impulse Acceleration, Mitrion, Mentor Graphics

  • Developed an FPGA aware version of GDB

    Capable of debugging the FPGA and System Software

    Capable of multiple CPUs and multiple FPGAs

  • Developed RASC Abstraction Layer (RASCAL)


Software overview

Software Overview

Download

Utilities

Debugger (GDB)

Application

User Space

Abstraction Layer

Library

Device

Manager

Algorithm Device Driver

Download Driver

Linux Kernel

COP (TIO, Algorithm FPGA, Memory, Download FPGA)

Hardware


Abstraction layer algorithm api

Abstraction Layer: Algorithm API

Algorithm

Application

Input Data

COP

Input Data

Algorithm

Output Data

Output Data

COP

COP

COP

COP

Application

  • The Abstraction Layer’s algorithm API mirrors the COP API with a few additions that enable wide scaling,

  • and deep scaling.


Hardware

Hardware

  • Direct Connection to NUMAlink4

  • 6.4GB/s/connection

  • Fast System Level Reprogramming of FPGA

  • Atomic Memory Operations

    Same set as System CPUs

  • Hardware Barriers

  • Configurations to 8191 NUMA/FPGA connections


Moatb block diagram

MOATB Block Diagram

2MB

QDR SRAM

Addr & Ctrl

36

36

Addr & Ctrl

Addr & Ctrl

Algorithm

FPGA

36

36

2MB

QDR SRAM

2MB

QDR SRAM

36

36

Select Map

Programming Interface

Loader

FPGA

SSP

72

72

TIO

PCI 66MHz

NUMAlink Connectors

NUMAlink12.8 GB/s

SSP 6.4 GB/s

QDR SRAM 9.6GB/s

3 reads @ 1.6GB/s

3 writes @ 1.6GB/s


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