1 / 45

# Logic Design Review – 1 Basic Gates - PowerPoint PPT Presentation

Logic Design Review – 1 Basic Gates. Lecture L14.1 Verilog. Basic Gates. NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate. Y. X. 0 1. 1 0. Basic Gates. Y = ~X not (Y , X). X. Y. NOT. X Y Z 0 0 0 0 1 0 1 0 0 1 1 1. Z = X & Y

I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.

## PowerPoint Slideshow about ' Logic Design Review – 1 Basic Gates' - callum-kramer

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

### Logic Design Review – 1Basic Gates

Lecture L14.1

Verilog

• NOT Gate

• AND Gate

• OR Gate

• XOR Gate

• NAND Gate

• NOR Gate

• XNOR Gate

X

0

1

1

0

Basic Gates

Y = ~X

not(Y,X)

X

Y

NOT

X Y Z

0 0 0

0 1 0

1 0 0

1 1 1

Z = X & Y

and(Z,X,Y)

X

AND

Z

Y

X Y Z

0 0 0

0 1 1

1 0 1

1 1 1

Z = X | Y

or(Z,X,Y)

X

OR

Z

Y

Any logic circuit can be created using only these three gates

X

~X

~~X = X

X ~X ~~X

0 1 0

1 0 1

Behavior:

The output of a NOT gate is the inverse (one’s complement) of the input

Behavior:

The output of an AND gate is HIGH only if all inputs are HIGH

assign Z = X[1] & X[2] & ... & X[n];

assign Z = &X;

and(Z,X[1],X[2],...,X[n]);

3-Level

Behavior:

Z = X[1];

for(i=2; i<=4; i++)

Z = Z & X[i];

2-Level

Behavior:

The output of an OR gate is LOW only if all inputs are LOW

assign Z = X[1] | X[2] | ... | X[n];

assign Z = |X;

or(Z,X[1],X[2],...,X[n]);

3-Level

Behavior:

Z = X[1];

for(i=2; i<=4; i++)

Z = Z | X[i];

2-Level

Behavior:

The output of an XOR gate is HIGH

only if the number of HIGH inputs is ODD

assign Z = X[1] ^ X[2] ^ ... ^ X[n];

assign Z = ^X;

xor(Z,X[1],X[2],...,X[n]);

Z

Y

2-Input XOR Gate

XOR

X Y Z

0 0 0

0 1 1

1 0 1

1 1 0

Z = X ^ Y

xor(Z,X,Y)

Note:

if Y = 0, Z = X

if Y = 1, Z = ~X

Therefore, an XOR gate can be used

as a controlled inverter

3-Level

Behavior:

Z = X[1];

for(i=2; i<=4; i++)

Z = Z ^ X[i];

2-Level

Note: Z = 1 if the number of 1 inputs in ODD

Exclusive-NOR Gate XNOR (NOT – XOR)

Behavior:

The output of an XNOR gate is HIGH

only if the number of HIGH inputs is EVEN

assign Z = ~(X[1] ^ X[2] ^ ... ^ X[n]);

assign Z = ~^X;

xnor(Z,X[1],X[2],...,X[n]);

XNOR

X Y Z

0 0 1

0 1 0

1 0 0

1 1 1

X

Z

Y

Z = ~(X ^ Y)

Z = X ~^ Y

xnor(Z,X,Y)

Note: Z = 1 if X = Y

Therefore, an XNOR gate can be used

as an equality detector

Behavior:

The output of an NAND gate is LOW only if all inputs are HIGH

assign Z = ~(X[1] & X[2] & ... & X[n]);

assign Z = ~&X;

nand(Z,X[1],X[2],...,X[n]);

NAND

X Y Z

0 0 1

0 1 1

1 0 1

1 1 0

X

Z

Y

Z = ~(X & Y)

Z = X ~& Y

nand(Z,X,Y)

Behavior:

The output of an NOR gate is HIGH only if all inputs are LOW

assign Z = ~(X[1] | X[2] | ... | X[n]);

assign Z = ~|X;

nor(Z,X[1],X[2],...,X[n]);

NOR

X Y Z

0 0 1

0 1 0

1 0 0

1 1 0

X

Z

Y

Z = ~(X | Y)

Z = X ~| Y

nor(Z,X,Y)

module gates ( X ,Z, Y );

input [4:1] X ;

wire [4:1] X ;

output [6:1] Z ;

wire [6:1] Z ;

output [6:1] Y ;

wire [6:1] Y ;

and(Z[6],X[1],X[2],X[3],X[4]);

nand(Z[5],X[1],X[2],X[3],X[4]);

or(Z[4],X[1],X[2],X[3],X[4]);

nor(Z[3],X[1],X[2],X[3],X[4]);

xor(Z[2],X[1],X[2],X[3],X[4]);

xnor(Z[1],X[1],X[2],X[3],X[4]);

assign Y[6] = &X;

assign Y[5] = ~&X;

assign Y[4] = |X;

assign Y[3] = ~|X;

assign Y[2] = ^X;

assign Y[1] = ~^X;

endmodule

Verilog gate level primitives

Verilog reduction operators

and(Z[6],X[1],...

nand(Z[5],X[1], ...

or(Z[4],X[1], ...

nor(Z[3],X[1], ...

xor(Z[2],X[1], ...

xnor(Z[1],X[1], ...

assign Y[6] = &X;

assign Y[5] = ~&X;

assign Y[4] = |X;

assign Y[3] = ~|X;

assign Y[2] = ^X;

assign Y[1] = ~^X;

X

Z

X

Z

=

Y

Y

Z = ~(X & Y)

Z = ~X | ~Y

X Y W Z

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

X Y ~X ~Y Z

0 0 1 1 1

0 1 1 0 1

1 0 0 1 1

1 1 0 0 0

~(X | Y) = ~X | ~Y

• NOT all variables

• Change & to | and | to &

• NOT the result

X

X

Z

Z

Y

Y

Z = ~(X | Y)

Z = ~X & ~Y

X Y Z

0 0 1

0 1 0

1 0 0

1 1 0

X Y ~X ~Y Z

0 0 1 1 1

0 1 1 0 0

1 0 0 1 0

1 1 0 0 0

~(X | Y) = ~X & ~Y

• NOT all variables

• Change & to | and | to &

• NOT the result

• NOT all variables

• Change & to | and | to &

• NOT the result

• --------------------------------------------

• ~X | ~Y = ~(~~X & ~~Y) = ~(X & Y)

• ~(X & Y) = ~~(~X | ~Y) = ~X | ~Y

• ~X & ~Y = ~(~~X | ~~Y) = ~(X | Y)

• ~(X | Y) = ~~(~X & ~Y) = ~X & ~Y

module gates ( X ,Z);

input [4:1] X ;

wire [4:1] X ;

output [1:6] Z ;

reg [1:6] Z ;

integer i;

// 4-input and gate

always @(X)

begin

Z[1] = X[1];

for(i=2; i<=4; i=i+1)

Z[1] = Z[1] & X[i];

end

// 4-input nand gate -- DeMorgan's Theorem

always @(X)

begin

Z[2] = ~X[1];

for(i=2; i<=4; i=i+1)

Z[2] = Z[2] | ~X[i];

end

=

// 4-input or gate

always @(X)

begin

Z[3] = X[1];

for(i=2; i<=4; i=i+1)

Z[3] = Z[3] | X[i];

end

// 4-input nor gate

// DeMorgan's theorem

always @(X)

begin

Z[4] = ~X[1];

for(i=2; i<=4; i=i+1)

Z[4] = Z[4] & ~X[i];

end

// 4-input xor gate

always @(X)

begin

Z[5] = X[1];

for(i=2; i<=4; i=i+1)

Z[5] = Z[5] ^ X[i];

end

// 4-input xnor gate

always @(X)

begin

Z[6] = X[1];

for(i=2; i<=4; i=i+1)

Z[6] = Z[6] ~^ X[i];

end

endmodule

nand

or

nor

xor

xnor

A

Relays

A

A

C

C

C

B

B

pMOS transistor

A-B closed when

C = 0

(normally closed)

nMOS transistor

A-B closed when

C = 1

(normally open)

B

Normally open

Normally closed

Y

X

0

1

1

0

X

Y

NOT Gate

Y

X

Y = ~X

not(Y,X)

Y

X

0

1

1

0

X

Y

NOT Gate

Y

X

0

1

Y = ~X

not(Y,X)

Y

X

0

1

1

0

X

Y

NOT Gate

Y

X

1

0

Y = ~X

not(Y,X)

5V

Z

X

Z

Y

X

X Y Z

0 0 1

0 1 1

1 0 1

1 1 0

Y

5V

Z

X

Z

0

Y

X

X Y Z

0 0 1

0 1 1

1 0 1

1 1 0

0

Y

5V

Z

X

Z

0

Y

X

X Y Z

0 0 1

0 1 1

1 0 1

1 1 0

1

Y

5V

Z

X

Z

1

Y

X

X Y Z

0 0 1

0 1 1

1 0 1

1 1 0

0

Y

5V

Z

X

Z

1

Y

X

X Y Z

0 0 1

0 1 1

1 0 1

1 1 0

1

Y

5V

X

X

Z

Y

Y

Z

X Y Z

0 0 1

0 1 0

1 0 0

1 1 0

5V

0

X

X

Z

Y

0

Y

Z

X Y Z

0 0 1

0 1 0

1 0 0

1 1 0

5V

0

X

X

Z

Y

1

Y

Z

X Y Z

0 0 1

0 1 0

1 0 0

1 1 0

5V

1

X

X

Z

Y

0

Y

Z

X Y Z

0 0 1

0 1 0

1 0 0

1 1 0

5V

1

X

X

Z

Y

1

Y

Z

X Y Z

0 0 1

0 1 0

1 0 0

1 1 0

Z

AND Gate

5V

X

NAND-NOT

Y

Z

OR Gate

5V

NOR-NOT

X

Y