A non volatile flip flop in magnetic fpga chip
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A non-volatile Flip-Flop in Magnetic FPGA chip. W.Zhao, E. Belhaire, V. Javerliac, C. Chappert, B. Dieny. Design and Test of Integrated Systems in Nanoscale Technology,. pp.323-326, 2006. 指導老師 : 魏凱城 老師 學 生 : 蕭荃泰 日 期 : 97 年 4 月 14 日. 彰化師範大學積體電路設計研究所. Outline. Abstract

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A non-volatile Flip-Flop in Magnetic FPGA chip

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A non volatile flip flop in magnetic fpga chip

A non-volatile Flip-Flop in Magnetic FPGA chip

W.Zhao, E. Belhaire, V. Javerliac, C. Chappert, B. Dieny

Design and Test of Integrated Systems in Nanoscale Technology,

pp.323-326, 2006

指導老師: 魏凱城 老師

學 生: 蕭荃泰

日 期: 97年4月14日

彰化師範大學積體電路設計研究所


Outline

Outline

  • Abstract

  • Magnetic Flip-Flop

  • Magnetic Standard Non-Volatile Flip-Flop

  • MSFlip-Flop Simulation

  • Conclusion


Abstract

Abstract

  • The propose a non-volatile flip-flop, which presents simultaneously low power dissipation and high speed.

  • This flip-flop is based on MRAM (Magnetic RAM) technology on standard CMOS.

  • In this non-volatile flip-flop design, we use Magnetic Tunnel Junctions (MTJ) as storage element.

  • In this paper, a magnetic flip-flop is proposed to make the FPGA circuit completely non-volatile.


Magnetic flip flop

Magnetic Flip-Flop

  • Magnetic tunnel junction (MTJ) structure consisting

    of two ferromagnetic metals separated by a thin

    insulating layer.

Fig1. the position of MTJs


A non volatile flip flop in magnetic fpga chip

Fig2. SRAM based Master-Slave

Flip-Flop structure

Fig3. Magnetic Flip-Flop structures


A non volatile flip flop in magnetic fpga chip

Fig4. schema of SRAM based sense amplifier


A non volatile flip flop in magnetic fpga chip

0

1

0

1

1

0

0

1

Fig5. Magnetic writing circuits


A non volatile flip flop in magnetic fpga chip

The simulation of magnetic Flip-Flop


Magnetic standard non volatile flip flop

Magnetic Standard Non-Volatile Flip-Flop

(b)

(a)

Fig6. (a) Magnetic Standard mixed Flip-Flop schema

(b) Magnetic Standard mixed Flip-Flop symbol


Msflip flop simulation

MSFlip-Flop Simulation

  • In the magnetic-standard flip-flop simulation, the low frequency control signal “NW” is 10 KHz, the clock frequency is 500MHz and the input frequency is 250MHz.

  • 130nm technologies have been used for the CMOS part, and a completesimulation model has been developed by CEA for the magnetic part.


A non volatile flip flop in magnetic fpga chip

Fig7. The simulation results of magnetic standard non-volatile Flip-Flop.

The last Data saved in MTJ is ‘1’


A non volatile flip flop in magnetic fpga chip

Fig8. The simulation results of magnetic standard non-volatile Flip-Flop.

The last Data saved in MTJ is ‘0’


A non volatile flip flop in magnetic fpga chip

The flip-flop keeps the non-volatility of 1/X times

(X is the ratio of processing frequency and the low,

user defined frequency)


Conclusion

Conclusion

  • We proposed this new architecture of Magnetic Standard flip-flop which features simultaneously non-volatility, high speed and low power dissipation.

  • This flip-flop can also be used to replace all the registers in SOC (System-on-chip) then makes these chips non-volatile and secure.


The end

The end


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