A Foundation Architecture for Elevating DSP in FPGAs

1. A Foundation Architecture for Elevating DSP in FPGAs Presented by Allan Cantle - Nallatech Ltd

2. Agenda • Scene Setting - DSP Architectures • DIME Overview • DIME Configuration and Interface Tools that enhance the usability of DSP in FPGAs • Real Example of DIME in action • Summary

3. The Architecture Playing Field is Changing! • Traditional - Generic Hardware approach DSP Main Processor DSP Coprocessor Field Programmable Gate Array FPGA Coprocessor FPGA Main processor • Future - DSP’s will disappear with complete algorithms compiled directly to FPGAs • Today - The FPGA is often Central to the system and the DSP is a coprocessor

4. What is Facilitating this DSP to FPGA Shift • FPGAs have taken a leap forward in their capacity making them viable for serious DSP applications • Base Level language - VHDL & Verilog • Software Engineer accessibility with C compiling directly to FPGAs • Next Generation - e.g. MATLAB to FPGA compilers

5. Real World DSP Example • Modelling an Optical Transfer Function • 1024x1024 x 100Hz Image with 16 bit data widths • 13 x 13 Convolver with 16 bit Datapath and Coefficients running at 128MHz • 43 Billion Operations Per Second, BOPS • Achievable in 1.5 XCV1000 Virtex FPGAs • TI C6 feature 0.6 - 1.2 BOPS - Not Deterministic • Doesn’t Include getting data in and out of C6 • At least 36 C6 processors to perform this operation • Obviously not practical

6. What is Facilitating the Architecture Shift • Nothing - Until now • Why? • Several Module Standards • TRAM, HTRAM, TIM40, SHARCPAC • PMC, PC-MIP • No standard provision for FPGA control • Lack of support for generic nature of FPGAs • I/O Limitations

7. DIME a Modular Hardware Platform for DSP systems D I M E SP and mage Processing odule for nhanced FPGAs

8. DIME - Leveraging the FPGA Advantage • A Modular Systems Approach • Complex Systems Construction • Module I/O Bandwidths over 2GBytes/Sec • Deterministic Data Processing • Support for Standard DSPs • Dynamic Reconfiguration of FPGAs Directly from Host • Plug‘n’Play FPGA Infrastructure

9. DIME - Physical & Virtual • Physical, Level 0 DIME Specification • Mechanical & Electrical Specification • Clocks, FPGA & DSP ICE JTAG chains • Over 200 unspecified user I/O Pins • Virtual, Level 1 DIME Specification • Rigid Definition of I/O Pin Functionality • Can be Many Different Level 1 Standards to suit different application areas

10. DIME Module Outline I/O Connectors Adjacent DIME Module Adjacent DIME Module FPGA FPGA FPGA DIME Connectors

11. Toolbar Board Level Module Level Log and status window. Device Level Pop up window providing device options for configuration Graphical Representation of Ballynuey Board Dynamic FPGA Configuration

12. Real World DSP Example • Modelling an Optical Transfer Function • 1024x1024 x 100Hz Image with 16 bit data widths • 13 x 13 Convolver with 16 bit Datapath and Coefficients running at 128MHz • 43 Billion Operations Per Second, BOPS • Achievable in 1 DIME Module • TI C6 feature 0.6 - 1.2 BOPS - Not Deterministic • Doesn’t Include getting data in and out of C6 • At least 36 C6 processors to perform this operation • Obviously not practical

13. Examples of Particle Method Implemented using DIME

14. Summary • Introduced DIME the new module standard that enables the power of Distributed DSP in FPGAs • Illustrated development tools for creating DIME based systems • Demonstrated real world applications that can be achieved with DIME.