1 / 30

Instructor: Dr. Phillip Jones (phjones@iastate) Reconfigurable Computing Laboratory

ECpE 583 Reconfigurable Computing Lecture 22: Tue 11/11/2008 (Placing Applications onto FPGAs: Part III). Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://www.ece.iastate.edu

calida
Download Presentation

Instructor: Dr. Phillip Jones (phjones@iastate) Reconfigurable Computing Laboratory

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. ECpE 583Reconfigurable ComputingLecture 22: Tue 11/11/2008(Placing Applications onto FPGAs: Part III) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://www.ece.iastate.edu http://class.ece.iastate.edu/cpre583 (coming soon) http://www.arl.wustl.edu/~phjones/cpre583 (temporary)

  2. Class Announcements • Updated schedule (coming soon) • MP2 concerns • CPRE594: Embedded System Optimization

  3. Outline • Placing an application on an FPGA • Low-level details (Focus on Placement)

  4. Applications on FPGA • Low-level: Application to FPGA refs • Reconfigurable Computing (2008) • Scott Hauck, Andre DeHon • The VLSI handbook (2000) • Wai-Kai Chen (note: there’s a 2nd edition (2006)) • Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays • Jason Cong (TODAES’96)

  5. Applications on FPGA: Low-level • Implement circuit in VHDL (Verilog) • Simulate compiled VHDL • Synthesis VHDL into a device independent format • Map device independent format to device specific resources • Check that device has enough resources for the design • Place resources onto physical device locations • Route (connect) resources together • Completely routed • Circuit meets specified performance • Download configuration file (bit-steam) to the FPGA

  6. Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

  7. Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

  8. Place • Bind each mapped resource to a physical device location • User Guided Layout (Chapter 16:Reconfigurable Computing) • General Purpose (Chapter 14:Reconfigurable Computing) • Simulated Annealing • Partition-based • Structured Guided (Chapter 15:Reconfigurable Computing) • Data Path based • Heuristics used • No efficient means for finding an optimal solution

  9. Place (High-level) Netlist from technology mapping in A in B in C RAM E DFF F LUT D DFF G clk out

  10. Place (High-level) Netlist from technology mapping FPGA physical layout I/O I/O I/O I/O in A in B in C I/O BRAM I/O LUT LUT RAM E I/O I/O DFF F LUT D LUT I/O I/O LUT BRAM I/O LUT I/O LUT DFF G I/O I/O clk LUT I/O LUT I/O out I/O I/O I/O I/O

  11. Place (High-level) Netlist from technology mapping FPGA physical layout clk in C out I/O in A in B in C In A E I/O LUT G D F RAM E In B I/O DFF F LUT D LUT I/O I/O LUT BRAM I/O LUT I/O LUT DFF G I/O I/O clk LUT I/O LUT I/O out I/O I/O I/O I/O

  12. Place (User-Guided) • User provide information about applications structure to help guide placement • Can help remove critical paths • Can greatly reduce amount of time for routing • Several methods to guide placement • Fixed region • Floating region • Exact location • Relative location

  13. Place (User-Guided): Examples Part of Map Netlist DFF F LUT D DFF G FPGA Fixed region

  14. Place (User-Guided): Examples Part of Map Netlist DFF F SDRAM LUT D DFF G FPGA Fixed region

  15. Place (User-Guided): Examples Floating region FPGA Softcore Processor

  16. Place (User-Guided): Examples Part of Map Netlist DFF F LUT D DFF G FPGA Exact Location LUT BRAM LUT LUT LUT LUT LUT LUT LUT BRAM LUT LUT LUT LUT LUT LUT LUT LUT

  17. Place (User-Guided): Examples Part of Map Netlist DFF F LUT D DFF G FPGA Exact Location LUT BRAM LUT LUT G LUT D F LUT LUT LUT BRAM LUT LUT LUT LUT LUT LUT LUT LUT

  18. Place (User-Guided): Examples Part of Map Netlist G DFF F D F LUT D DFF G FPGA Relative Location LUT BRAM LUT LUT LUT LUT LUT LUT LUT BRAM LUT LUT LUT LUT LUT LUT LUT LUT

  19. Place (User-Guided): Examples Part of Map Netlist G DFF F D F LUT D DFF G FPGA Relative Location LUT BRAM LUT LUT LUT LUT LUT LUT LUT BRAM LUT LUT LUT LUT LUT LUT LUT LUT

  20. Place (User-Guided): Examples Part of Map Netlist G DFF F D F LUT D DFF G FPGA Relative Location LUT BRAM LUT LUT LUT LUT LUT LUT LUT BRAM LUT LUT LUT LUT LUT LUT LUT LUT

  21. Place (General Purpose) • Characteristics: • Places resources without any knowledge of high level structure • Guided primarily by local connections between resources • Drawback: Does not take explicit advantage of applications structure • Advantage: Typically can be used to place any arbitrary circuit

  22. Place (General Purpose) • Preprocess Map Netlist using Clustering • Group netlist components that have local conductivity into a single logic block • Clustering helps to reduce the number of objects a placement algorithm has to explicitly place.

  23. Place (General Purpose) • Placement using Simulated Annealing • Based on the physical process of annealing used to create metal alloys

  24. Place (General Purpose) • Simulated annealing basic algorithm • Placement_cur = Inital_Placement; • T = Initial_Temperature; • While (not exit criteria 1) • While (not exit criteria 2) • Placement_new = Modify_placement(Placement_cur) • ∆ Cost = Cost(Placement_new) – Cost(Placement_cur) • r = random (0,1); • If r < e^(-∆Cost / T), Then Placement_cur = Placement_new • End loop • End loop

  25. Place (General Purpose) • Simulated annealing: Illustration

  26. Place (General Purpose) • Placement using partitioning

  27. Place (Structured-based) • Automatically leverage structure of the application • Algorithms my work well for a give structure, but will likely give unacceptable results for an design with little regular structure.

  28. Place (Structure-based) • Datapath-based example

  29. Next Lecture • Finish Placing Applications on FPGAs • Compute Models: Part I • Recommended Reading • Design Patterns for Reconfigurable Computing • http://ic.ese.upenn.edu/abstracts/despat_fccm2004.html

  30. Questions/Comments/Concerns • Write down • Main point of lecture • One thing that’s still not quite clear • If everything is clear, then give an example of how to apply something from lecture OR

More Related