Loading in 5 sec....

NAME: RIBADIYA RUPAL (130420107050) SUBJECT: BASIC ELECTRONICS PROJECT TITLE: Basic Logic GatesPowerPoint Presentation

NAME: RIBADIYA RUPAL (130420107050) SUBJECT: BASIC ELECTRONICS PROJECT TITLE: Basic Logic Gates

Download Presentation

NAME: RIBADIYA RUPAL (130420107050) SUBJECT: BASIC ELECTRONICS PROJECT TITLE: Basic Logic Gates

Loading in 2 Seconds...

- 176 Views
- Uploaded on
- Presentation posted in: General

NAME: RIBADIYA RUPAL (130420107050) SUBJECT: BASIC ELECTRONICS PROJECT TITLE: Basic Logic Gates

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

NAME: RIBADIYA RUPAL (130420107050)SUBJECT: BASIC ELECTRONICSPROJECT TITLE: Basic Logic Gates

SARVAJANIC COLLAGE OF ENGINEERING & TECHNOLOGY

- NOT, AND, and OR Gates
- NAND and NOR Gates
- DeMorgan’s Theorem
- Exclusive-OR (XOR) Gate
- Multiple-input Gates

NOT Gate -- Inverter

Y

X

0

1

1

0

- Y = ~X (Verilog)
- Y = !X (ABEL)
- Y = not X (VHDL)
- Y = X’
- Y = X
- Y = X (textook)
- not(Y,X) (Verilog)

X

~X

~~X = X

X ~X ~~X

0 1 0

1 0 1

AND

X Y Z

0 0 0

0 1 0

1 0 0

1 1 1

X

Z

Y

Z = X & Y

- X & Y (Verilog and ABEL)
- X and Y (VHDL)
- X Y
- X Y
- X * Y
- XY(textbook)
- and(Z,X,Y)(Verilog)

V

U

OR

X Y Z

0 0 0

0 1 1

1 0 1

1 1 1

X

Z

Y

Z = X | Y

- X | Y(Verilog)
- X # Y(ABEL)
- X or Y(VHDL)
- X + Y(textbook)
- X V Y
- X U Y
- or(Z,X,Y) (Verilog)

- NOT, AND, and OR Gates
- NAND and NOR Gates
- DeMorgan’s Theorem
- Exclusive-OR (XOR) Gate
- Multiple-input Gates

NAND

X Y Z

0 0 1

0 1 1

1 0 1

1 1 0

X

Z

Y

Z = ~(X & Y)

nand(Z,X,Y)

NOT-AND

X Y W Z

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

X

W

Z

Y

W = X & Y

Z = ~W = ~(X & Y)

NOR

X Y Z

0 0 1

0 1 0

1 0 0

1 1 0

X

Z

Y

Z = ~(X | Y)

nor(Z,X,Y)

NOT-OR

X Y W Z

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

X

W

Z

Y

W = X | Y

Z = ~W = ~(X | Y)

- NOT, AND, and OR Gates
- NAND and NOR Gates
- DeMorgan’s Theorem
- Exclusive-OR (XOR) Gate
- Multiple-input Gates

X

Z

X

Z

=

Y

Y

Z = ~(X & Y)

Z = ~X | ~Y

X Y W Z

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

X Y ~X ~Y Z

0 0 1 1 1

0 1 1 0 1

1 0 0 1 1

1 1 0 0 0

~(X & Y) = ~X | ~Y

- NOT all variables
- Change & to | and | to &
- NOT the result

X

X

Z

Z

Y

Y

Z = ~(X | Y)

Z = ~X & ~Y

X Y Z

0 0 1

0 1 0

1 0 0

1 1 0

X Y ~X ~Y Z

0 0 1 1 1

0 1 1 0 0

1 0 0 1 0

1 1 0 0 0

~(X | Y) = ~X & ~Y

- NOT all variables
- Change & to | and | to &
- NOT the result

- NOT all variables
- Change & to | and | to &
- NOT the result
- --------------------------------------------
- ~X | ~Y = ~(~~X & ~~Y) = ~(X & Y)
- ~(X & Y) = ~~(~X | ~Y) = ~X | ~Y
- ~X & !Y = ~(~~X | ~~Y) = ~(X | Y)
- ~(X | Y) = ~~(~X & ~Y) = ~X & ~Y

- NOT, AND, and OR Gates
- NAND and NOR Gates
- DeMorgan’s Theorem
- Exclusive-OR (XOR) Gate
- Multiple-input Gates

XOR

X Y Z

X

Z

0 0 0

Y

0 1 1

Z = X ^ Y

xor(Z,X,Y)

1 0 1

1 1 0

- X ^ Y(Verilog)
- X $ Y(ABEL)
- X @ Y
- xor(Z,X,Y) (Verilog)

XNOR

X Y Z

X

Z

0 0 1

Y

0 1 0

Z = ~(X ^ Y)

Z = X ~^ Y

xnor(Z,X,Y)

1 0 0

1 1 1

- X ~^ Y(Verilog)
- !(X $ Y)(ABEL)
- X @ Y
- xnor(Z,X,Y) (Verilog)

BASIC LOGIC GETS & BESIC DIGITAL GESIGN

NOT, AND, and OR Getes

NAND and NOR Getes

DeMorgan’s Theorem

Exclusive-OR(XOR) Gete

Multiple input Getes

Z

Z

2

1

Z

Z

4

3

Z

1

Output is HIGH only if all inputs are HIGH

Z

1

An open input will float HIGH

Z

2

Output is LOW only if all inputs are LOW

Z

2

Z

3

Output is LOW only if all inputs are HIGH

Z

3

Z

4

Output is HIGH only if all inputs are LOW

Z

4