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The history of Integrated Circuit (IC) The base for such a significant progress Well understanding of semiconductor physics Capability of purifying the material Fine control of IC manufacture process One of the most important inventions in our modern life IC has changed our life

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The history of Integrated Circuit (IC)

The base for such a significant progress

Well understanding of semiconductor physics

Capability of purifying the material

Fine control of IC manufacture process

One of the most important inventions in our modern life

IC has changed our life

Personal computer

Cellular phone

Internet

Wireless communication

Automobile electronics

Medical applications




Moore integrated circuit.’s law

  • The performance and density are doubled every 18 months.

  • Moore’s law has held for the past 40 year. Let’s look at

    • Moore’s law in microprocessors

    • Moore’s law in chip capacity

    • Die size growth

    • Wafer size (12 inch)


Moore s law in microprocessors

1000 integrated circuit.

2X growth in 1.96 years!

100

10

P6

Pentium® proc

486

1

Transistors (MT)

386

0.1

286

8086

8085

0.01

8080

8008

4004

0.001

1970

1980

1990

2000

2010

Year

Moore’s Law in Microprocessors

Courtesy, Intel


Evolution in dram chip capacity

human memory integrated circuit.

human DNA

book

encyclopedia

2 hrs CD audio

30 sec HDTV

page

Evolution in DRAM Chip Capacity

4X growth every 3 years!

0.07 m

0.1 m

0.13 m

0.18-0.25 m

0.35-0.4 m

0.5-0.6 m

0.7-0.8 m

1.0-1.2 m

1.6-2.4 m


Die size growth

100 integrated circuit.

P6

Pentium ® proc

486

10

Die size (mm)

386

286

8080

8086

~7% growth per year

8085

8008

~2X growth in 10 years

4004

1

1970

1980

1990

2000

2010

Year

Die Size Growth

Courtesy, Intel



Technology has moved into the deep submicron (DSM) feature size

  • The state of the art technology is 22nm feature size

  • Face many new IC design issues due to the increasing performance requirement and DSM feature size

    • Design for manufacture (DFM)

    • New device model

    • Performance driven design

    • Distributed circuit parameters

    • Power dissipation

    • More powerful CAD tools


Exploding mask costs

Data size

16GB

64GB

256GB

1024GB

Exploding Mask Costs

  • Raster scan patterning exposure time for a 110mm x 110 mm mask is 6.5 hrs and 20 hrs with fine granularities (60nm vs. 120nm pixel size)

  • Largest cost contribution to mask making is mask exposure time (capital cost ~$20M)

  • RET is being absorbed by CAD vendors into layout verification / tape-out suites.

  • RET may move up into routing, placement

Year

1999

2002

2004

2007

Node

.18µm

.13µm

.9µm

.065µm

Cost

$200-400K

$500K-1M

$800K-1.2M

$1-2M

Source: Thomas Weisel Partners


Power dissipation
Power Dissipation size

100

P6

Pentium ® proc

10

486

286

8086

Power (Watts)

386

8085

1

8080

8008

4004

0.1

1971

1974

1978

1985

1992

2000

Year

Power delivery and dissipation will be prohibitive

Courtesy, Intel


Power density

10000 size

1000

Rocket

Nozzle

100

Nuclear

Power Density (W/cm2)

Reactor

8086

10

4004

P6

Hot Plate

8008

Pentium® proc

8085

386

286

486

8080

1

1970

1980

1990

2000

2010

Year

Power Density

Power density too high to keep junctions at low temp

Courtesy, Intel


Custom and semi-custom ICs size

  • Custom designed microprocessors, such as Intel Pentium

  • Semi-custom designed ICs, such as gate array and FPGA

    • Specific circuit structures are introduced to shorten design cycle

    • Tread-off between the design quality and design time

    • ASIC chip usually uses custom design to increase the performance and to reduce the chip cost

    • Prototype development usually use the semi-custom design to reduce the design cycle



Design flow size

  • Traditional design flow

    • The design tasks usually can be divided into separated stages

    • Single direction, usually a top-down strategy

  • The interplay between different design tasks becomes important

    • Physical phenomena and circuit facts should be considered at high design levels

      • Floorplanning is a challenge


This chart only presents the basic tasks in the design process.

However, the flow of design tasks is not a single direction.

The influence of the late design stage can affect the early ones.



CAD tools process.

  • Most of today’s IC design are done by using CAD tools. The major CAD tools are:

    • Cadence

      • good physical design

      • synthesis

    • Synopsis

      • good high level synthesis

      • physical layout

    • Mentor Graphics

      • analog IC

      • verification

    • Magma

      • physical design, good in time closure


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