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Technion – Israel Institute of Technology Faculty of Electrical Engineering High Speed Digital System Lab (HS DSL). Exploring new implementation tools for GIDEL PROCSTAR platform ( Characterization presentation). Elad Hadar Omer Norkin Supervisor: Mike Sumszyk Winter 2010/11 Date:.
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Technion – Israel InstituteofTechnologyFacultyofElectricalEngineeringHigh Speed Digital System Lab (HS DSL) Exploring new implementation tools for GIDELPROCSTARplatform(Characterization presentation) EladHadar Omer Norkin Supervisor: Mike Sumszyk Winter 2010/11 Date:
Motivation • Implementing simple video analysis designs on GIDEL PROCSTAR III platform that will enable usage and exploration of new platform dedicated development tools. • Proper usage of development tools throughout all stages of implementation from algorithm to hardware. • Usage of powerful debug tools as part of the workflow.
Development & debug tools • GIDEL PROC HILs - enable HW acceleration under SIMULINK environment. • GIDEL PROC API – enable real-time configuration and querying of the board. • GIDELTOTAL HISTORY (based on ALTERAs SignalTap) – provide true tracing capabilities.
Project objective Implementation of a simple algorithm of computer vision performing edge detection using gradient computation in DSPbuilder.* Phase I Phase II Testing of the algorithm with Hardware in the loop (GidelPROC HILs) Partial porting to the FPGA Learning and practice of effective debug methodology using PROC API and Total History/SignalTap. * Two different algorithms will be implemented
Hardware • GiDEL'sPROCStar III is an ALTERA Stratix III based board. • 4xFPGA integrated on single board.
Workflow PROC HILs PROC API Total History/ Signal Tap
Workflow (phase I) • Simple algorithm code. • Stream-based implementation. • Simulinkdesigns based on ALTERA IPs. • Load the design on FPGA using • PROC HILs – • Analyzing tool’s performance.
Workflow (phase II) • Simple algorithm code. • Stream-based implementation. • Simulinkdesigns based on ALTERA IPs. • Automatic generation of VHDL/Verilog scripts based on a block design. • Perform Synthesis & Place and Route.
Workflow (phase II) • Generate interface envelope (VHDL code) • Create a project including all VHDL files (from DSPbuilder as well as from Procwizard) • Load the design on the FPGAs and apply PROC API functions to create an effective real time debug environment combined with ToatalHistory / Signal Tap.
Video stream diagram (phase II) PROC MegaFIFO RX - FIFO TX - FIFO PROC API
Full project plan • Learning the work environment (Simulink, DSPBuilder, Quartus, PROC Wizard, PROC Hils) • Implement the basic algorithm of gradient computation using DSPbuilder in Simulink environment • Testing the design using PROC Hils and analyzing prformance • Build a simple hardware design (Adder) combining DSPbuilder and the PROC Wizard • Learning Total history,PROCAPI, PROCMegaFIFO • Build an Adder design combining DSPbuilder and the PROC Wizard using PROC API • Define an integrated design combining PROC API video streaming functions and data channels, PROCMegaFIFO memories and DSPbuilder design • Real-time debug with Total history and Signal Tap (comparison of the tools)
