chapter 13
Download
Skip this Video
Download Presentation
Chapter 13

Loading in 2 Seconds...

play fullscreen
1 / 14

Chapter 13 - PowerPoint PPT Presentation


  • 161 Views
  • Uploaded on

Chapter 13. Direct Memory Access (DMA). Chapter Objectives. Review and compare main types of I/O Introduce Direct Memory Access (DMA) I/O Explain basic DMA operation: HOLD, HLDA Introduce the 8237A programmable DMA controller (DMAC)

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' Chapter 13' - buffy


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
chapter 13

Chapter 13

Direct Memory Access (DMA)

slide2

Chapter Objectives

  • Review and compare main types of I/O
  • Introduce Direct Memory Access (DMA) I/O
  • Explain basic DMA operation: HOLD, HLDA
  • Introduce the 8237A programmable DMA controller (DMAC)
  • Describe various types, modes and applications of DMA data transfer
review of i o types
Review of I/O Types

1. Programmed I/O

I/O between memory and the I/O device is performed by the Processor: e.g. IN AL,DX

MOV [DI],AL; Transfer is through the mP - slow!

1.1 Polling/Handshaking I/O

Processor checks device readiness repeatedly, e.g. in a tight loop

1.2 Interrupt-driven I/O

Device signals its readiness by an interrupt. Processor performs I/O by executing an ISR. Otherwise processor is doing other useful work

2. Direct Memory Access (DMA)

- Avoids the slow speed of programmed I/O when moving large amounts of data between memory and a peripheral

- Data transfer is coordinated by a DMA controller-not the processor

- Avoids the bottleneck of having to channel data through the mP

- Uses the 3 mP buses, so the mP is unable to use them temporarily

- Speed is limited only by those of the memory and the DMAC

slide4
DMA
  • Direct Memory Access (DMA) is a method whereby the memory and I/O space of the microprocessor can be accessed directly without the intervention of the microprocessor or a program.
  • To request DMA access, the DMAC raises the HOLD input high.
  • The microprocessor responds by floating the 3 buses and raising HLDA high to indicate that a hold is in effect.
  • The DMAC can now use the 3 buses to do DMA transfers on them- bypassing the processor
slide5
During a HOLD, the microprocessor stops running the program and places its address, data, and control bus connections at their HiZ state. This in effect is the same as removing the microprocessor from its socket!
  • While the microprocessor is held, other devices are free to gain access to its memory and I/O space and transfer data directly using them
  • Usually this requires the use of a programmable DMAC chip: (Direct Memory Access Controller), e.g. the 8237A
slide6
HOLD is sampled during instruction execution while interrupt signals are sampled at the end of instructions
  • HOLD takes effect (HLDA generated) in a clock cycle or two

 So, Hold has a higher priority than interrupts

  • The only input with a higher priority than HOLD is the RESET input to the microprocessor.

DMA finished

Device Requests

DMA Transfer

I/P

DMA Request

Granted- mP has relinquished

control of the buses

O/P

dma applications
DMA Applications
  • Wherever large amounts of data need to be transferred fast between memory and an I/O peripheral device, e.g.

- Hard disk, CD

- Video memory to refresh display

- Sound cards

- Network cards

- Data acquisition boards

  • Also for row address generation by hardware to refresh large DRAMs fast
slide8

I/O

Write

Memory

Read

HOLD

C

Simultaneously !

Memory address

Generated by fast

Counters on the DMAC

dma control signals
DMA Control Signals
  • Because during a DMA both memory and an I/O device may be accessed simultaneously, the DMAC may need to generate:

- #MRDC and #IOWC (simultaneously) for memory to I/O device transfers

- #IORC and #MRWC (simultaneously) for I/O device to memory transfers

This was not necessary with programmed I/O as processor either accessed memory or an I/O device at any given time moving data between it and the processor

dmac interface
DMAC Interface

With HLDA

Active

  • Two types of DMA data transfers:
  • Sequential DMA:
  • Read then Write through the DMAC
  • Data rests in DMAC. Only M or IO
  • controls are needed at any given time
  • Simultaneous DMA:
  • Data moved directly between peripheral and memory. Both M & IO controls used at the same time

The DMAC is a

Programmable I/O device

for the microprocessor,

Just like the PPI, PIC,

UART, …

DMA activities by the DMAC

will be programmed into it by

the processor before hand

the 8237a programmable dmac
The 8237A Programmable DMAC

Address bus

(during DMA)

  • Four separate prioritized DMA channels (expandable by using multiple DMACs)
  • Transfer rates up to 1.6 M bytes/s
  • DMA transfers by the DMA channels are programmed a priori into the DMAC by

the processor

  • Can address 64KB of memory in one programming operation

 16-bit addresses

  • Allows the following DMA transfer

combinations:

    • Memory to peripheral
    • Peripheral to memory
    • Peripheral to peripheral
    • Memory to memory
  • No longer used on the PC in chip form nowadays- its functionality has been embedded into modern chip set ICs

On-chip

Address I/Ps

 16 I/O adrs

(Programming)

mP

  • - Data Bus
  • (during
  • Programng)
  • A8-A15
  • During DMA

For address

Counters

DMA

Device

programming the dmac
Programming the DMAC

(Only these 3 numbers are written into the DMAC)

dma modes byte burst block 3 bees
DMA Modes: Byte, Burst & Block (3 Bees!)

Bars show

duration

of DMAC

controlling

the buses

Only

for

a

byte

(buffer full)

(buffer full)

As long

As Device

Is Ready

(filling its buffer)

Block finished?

As long

as needed

to transfer the block

DMAC gets more greedy for bus control

Block: (multiple buffers)

Fill the buffer of a fast

Device several times

Burst: (a buffer-full of data)

Fill the buffer of a slow device once

Byte:

Un-buffered device

ad