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ECE 493T9 Real Time Embedded System Tutorial Set 3 June 10, Spring 2008

ECE 493T9 Real Time Embedded System Tutorial Set 3 June 10, Spring 2008. Basic ES Peripherals. Timer / Counter Intel 8253, MC62830, Timer Processors, Real-Time Clocks. Serial Ports SPI, I 2 C, M-Bus, RS232 Parallel Port DMA (To Be Covered in the future if needed). Timers.

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ECE 493T9 Real Time Embedded System Tutorial Set 3 June 10, Spring 2008

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  1. ECE 493T9Real Time Embedded SystemTutorial Set 3June 10, Spring 2008

  2. Basic ES Peripherals • Timer / CounterIntel 8253, MC62830, Timer Processors, Real-Time Clocks. • Serial PortsSPI, I2C, M-Bus, RS232 • Parallel Port • DMA (To Be Covered in the future if needed)

  3. Timers • A Must-Have for all the Synchronous Operations. • Pre-scalar:Divide the clock freq. down to the desired counting freq. • Phase-Lock Loop:Multiply the clock freq. up to the desired counting freq. Often available in FPGA. • Counter • I / O ControlCan provide more functionalities than just a timer interrupt generator. • Characterized by 2 Properties:1) Pre-scalar Value (Min Clock Freq.)2) Counter Size

  4. Intel 8253 Timer • 5 Modes • Mode 1: Interrupt on Termination Count • Mode 2: Programmable One-Shot • Mode 3: Rate Generator (Pulse Generator) • Mode 4: Square-Wave Generator – Software Generated Strobe • Mode 5: Square-Wave Generator – Hardware Generated Strobe • When Interrupts are generated from the Intel 8253 Timer, the interrupt signal does not have a dedicated output pin; instead, the OUT pin is often used as the interrupt output pin.

  5. MC62830 Timer • 24bit Timer • Higher Resolution than Intel 8253 • 5bit Pre-Scalar Drawback: • Designed to work with 8-bitprocessors => loading the timerrequires 4 cycles:1) Load 3 8-bit preload registers2) Reset Z flag to start countdown

  6. Timer Processor • Just like memory management and graphic processing, the timing operation can also get “emancipated” from the mother CPU, giving rise the Timer Processor. • Design Note:Use it only when your design really requires a pinpointing timing!!Each addition of an application-specific processor means an additional burden on your design budget.

  7. Real-Time Clocks • Rather than generating clock counts from timers, RT clocks keep track of timing in terms of current time and date. • With modern microprocessors running at MHz range, RT clocks can also be software simulated to effectively reduce the design cost.

  8. Serial Ports • Dominant data transfer method from ES to its peripherals • Two interconnected shift registers • Sync. and Async.

  9. Serial Peripheral Interface (SPI) • By Motorola • Synchronous Master-Slave System.

  10. Inter-IC Bus (I2C) • Developed by Philips in the 80s for IC components communication in TV. • Two-line serial bus (SCL, SDA) with Master / Slave Communication Mode. • Serial Control Line: (SCL)Carries controlled clock signal, used for both synchronizing and flow control. • Serial Data and Address: (SDA)Carries address and data; used in combination with SCL to facilitate flow control. • Basic Flow Control Mechanism:

  11. Inter-IC Bus (I2C) • Three Main Data Transfer Modes: • Read Byte with ACK • Write Byte with ACK • Write Byte with STOP

  12. Inter-IC Bus (I2C) • Multiple Slave Access:How to access a specific slave? Transfer Address before Data!! • Basic Access Procedure: • Extended Address Access Procedure:

  13. Inter-IC Bus (I2C) • Other Issues: • Multi-Register Transfer • Inheritant Address Increment • Write Index • ACK Flag Timing Issue • I2C Masters would need a timer to determine the length of a valid ACK flag. • Multi Master Access Regulation • When two or more masters are on the bus, they generally monitor the bus and wait until it’s clear before they attempt to initiate any bus activity.

  14. Recommended Standard 232 • Implemented with DSub9 port. • CMOS or TTL Voltage Standard. • +5V and -5V • +12V and -12V • Logical Voltage Tolerance: ±2V • RS232 is the physical interface on top of which serial transmission is facilitated via serial protocols(ex. DF1, ModBus, etc.). • Basic RS232 Packet (by Physical Layer Definition, ref. OSI Model)

  15. Recommended Standard 232 • Async. Flow Control Signal Lines • Fact: - The layout is outdated for most applications nowadays, since RS232 has not been used as a networking infrastructure for more than a decade. - Instead of utilizing all 9 lines, only TxD and RxD are being used for point-to-point data transfer – Very similar to USB. - Occasionally, some specialized chips (such as a CANbus Interface Chip ELM232 I’ve used for my FPGA project) would require RTS / CTS to facilitate simple handshaking- The rest signal lines are rarely used in new ES’s. If you ever need to use them, reference materials are all over the internet for grab.

  16. Recommended Standard 232 • How to Implement RS232 Interface? • Most uC’s come with at least one async. channel. • Connect the async. channel to a RS232 physical driver chip in order to conform to the voltage standard. • How about USB? • As mentioned previously, most USB chips have similar interface as the RS232 driver chip.

  17. About the Project…=( =( =( • Until we are 100% sure the dev kit will arrive in time, we will not have a tutorial on Atmel Processor User Manual. • One thing I’m sure about the project:It’s a simple design project without much constraints on the end-product to be delivered. • It doesn’t mean that you get to hand in a first-year level design!! It also doesn’t mean that the professor will be extra lenient on marking!! • Base your designs on RTOS concepts taught in this course to earn a decent mark.

  18. Questions? Questions? Questions?

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