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A CMOS Operational Amplifier with Constant 68° phase margin over its whole range of noise-power trade-off programmability.

brynn-miller
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  1. A CMOS Operational Amplifier with Constant 68° phase margin over its whole range of noise-power trade-off programmability Meier auf der Heide, P.; Bronskowski, C.; Tomasik, J.M.; Schroeder, D.;33rd European Solid State Circuits Conference, 2007. ESSCIRC11-13 Sept. 2007 Page(s):452 - 455 Digital Object Identifier 10.1109/ESSCIRC.2007.4430340 學 號: m97662001 學 生: 莊明龍 日 期: 97年11月17日 彰化師範大學積體電路設計研究所

  2. Outline • INTRODUCTION • ARCHITECTURE AND THEORY • REALISATION • MEASUREMENT RESULTS • CONCLUSION

  3. INTRODUCTION • Programmable OpAmps have the advantage of being adaptable to the given circuit specification. • At ESSCIRC 2006 ，experimental results showed a PM ：74° → 16° when power consumption 140 μW→30 mW, input noise ：14 nV/ √ Hz → 2 nV/√Hz • In this paper, an improved OpAmp architecture,which ensures a nearly constant phase margin over the whole range of programmability.

  4. ARCHITECTURE AND THEORY • Based on a rail-to-rail OpAmp. Bias currents for the active stages are generated in an extra bias circuit. • In principle, two bias currents must hold in order to obtain a phase margin that is independent of the operating point. Basically, quadratic relations between three stage are required. • In the original architecture it was impossible to satisfy these constraints exactly, as the bias currents in question were not independent of each other because of the circuit topology.

  5. ARCHITECTURE AND THEORY • Schematic of the improved OPAmp

  6. ARCHITECTURE AND THEORY • Schematic of the improved OPAmp

  7. REALISATION • The OpAmp realized in a 0.35 um CMOS technology. For simple, we chose this time to omit the chopper modulation. • First, basic design formulas were obtained from simple MOSFET models. • Second, the remaining design parameters were computed between chip area and power consumption at the low-noise point range. • The product of area & supply current was min. • Third, the W/L-ratios and the Miller capacitance obtained from this procedure were the starting point for the final dimensioning of the OpAmp with the help of simulations.

  8. REALISATION

  9. REALISATION • Relationship of bias currents

  10. REALISATION • Chip micrograph of OpAmp

  11. MEASUREMENT RESULTSA. Noise-Power Trade-Off • Input-referred thermal noise vs. power consumption

  12. MEASUREMENT RESULTSB. Phase Margin • Unity gain phase margin vs. power consumption.

  13. MEASUREMENT RESULTS • In order to further substantiate the stability properties of the OpAmp, we measured its step response in a voltage-follower configuration, which is the most critical one if stability is concerned. We found stable behaviour – i.e. not more than a single overshoot in the step response – on the low-power end of the programmability range (below 2 mW).

  14. CONCLUSION • A novel architecture for an operational amplifier with a programmable trade-off between low-noise and low-power operation . • The key to the solution was a decoupling of the quiescent bias currents in three stages, together with a corresponding biasing scheme. • The digital inputs can even be effectively used by a microcontroller or digital signal processor for an adaptive selection of the operating point.

  15. THE END

  16. REFERENCES • [1] L.P. Carloni, F. De Bernardinis, A.L. Sangiovanni-Vincentelli, M.Sgroi, “The art of integrated systems design,” in Proceedings 28th European Solid-State Circuits Conference (ESSCIRC 2002), Firenze, Italy, 24-26 September 2002, pp. 25-36. • [2] C. Bronskowski, D. Schroeder, A Programmable Analog Front End for the Aquisition of Biomedical Signals, Proceedings ProRISC 2004 Workshop, Veldhoven, The Netherlands, 25-26 November 2004, pp.474-477. • [3] C. Bronskowski, D. Schroeder, “An ultra low-noise operational amplifier with programmable noise-power trade-off,” in Proceedings 32nd European Solid-State Circuits Conference (ESSCIRC 2006), Montreux,Switzerland, 19-21 September 2006,pp. 368-371. • [4] R. Hogervorst, J.P. Tero, R.G.H. Eschauzier, J.H. Huijsing, “A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries,” IEEE J. Solid State Circuits, vol. 29, no. 12, pp. 1505-1513, 1994.

  17. REFERENCES • [5] J.H. Huijsing, R. Hogervorst, K.-J. de Langen, “Low-power lowvoltage VLSI operational amplifier cells,” IEEE Trans. on Circuits and Systems-I, vol. 42, no. 11, pp. 841-852, 1995. • [6] C. Bronskowski, D. Schroeder, “Systematic design of programmable operational amplifiers with noise-power trade-off,” IET Circuits, Devices & Systems, vol. 1 (2007), no. 1, pp. 41-48. • [7] C. Bronskowski, P. Meier auf der Heide, D. Schroeder, “Optimisation of programmable operational amplifiers,” in Proceedings ProRISC 2005 Workshop, Veldhoven, The Netherlands, 17-18 November 2005, pp. 195-200. • [8] Fairchild Semiconductor, “Board layout techniques for highperformance amplifiers,” Application Note AN-6039, 2006. • [9] N. Van Helleputte, A. Mora-Sanchez, W. Galjan, J.M. Tomasik, D. Schroeder, W. Krautschneider, R. Puers, “A flexible system-on-chip(SoC) for biomedical signal acquisition and processing,” in Proceedings Eurosensors XX, Goeteborg, Sweden, 17-20 September 2006.

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