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Adaptive Cache-Line Size Management on 3D Integrated Microprocessors

Adaptive Cache-Line Size Management on 3D Integrated Microprocessors. ISOCC 2009. Takatsugu Ono, Koji Inoue and Kazuaki Murakami Kyushu University, Japan. Outline. Introduction Software Controllable-Variable Line Size (SC-VLS) Cache Evaluation Summary. 3D Integration.

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Adaptive Cache-Line Size Management on 3D Integrated Microprocessors

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  1. Adaptive Cache-Line Size Management on 3D Integrated Microprocessors ISOCC 2009 Takatsugu Ono, Koji Inoue and Kazuaki Murakami Kyushu University, Japan

  2. Outline • Introduction • Software Controllable-Variable Line Size(SC-VLS) Cache • Evaluation • Summary

  3. 3D Integration • Stacking the main memory on processors • Connecting them by wide on-chip buses • The memory bandwidth can be improved

  4. Motivation • 3D stacking makes it possible to reduce the cache miss penalty • We can employ larger cache line size in order to expect the effect of prefetching • But… if programs don’t have high spatial localities of memory references • It might worsen the performance • A large amount of energy is required!

  5. Software-Controllable Variable Line-Size Cache (1/3) • We propose SC-VLS cache • It attempts to optimize the amount of data to be transferred between cache memory and main memory • When a program does not require high memory bandwidth 　⇒SC-VLS cache reduces the cache line size

  6. Software-Controllable Variable Line-Size Cache (2/3) • Features • SC-VLS cache doesn’t require any hardware monitor to decide the line size • Advantages • SC-VLS cache reduces energy consumption with trivial hardware overhead

  7. Software-Controllable Variable Line-Size Cache (3/3) • Adequate line size analysis • Before an application program is executed, we analyze an adequate line size of each function • Code generation • Line size change instructions are inserted into start of functions in original program code • The instruction sets status register to indicate an adequate line size

  8. Adequate Line Size Analysis- Example-

  9. Evaluation • Simulator • SimpleScalar and CACTI • Benchmark programs • 10 programs (MiBench) • Input data sets • Analysis phase: small • Execution phase: large • The SC-VLS cache can dynamically choose four line sizes; • 32B, 64B, 128B and 256B

  10. Energy 19.3 11.4 11.4 11.3 3.7 3.7 5.2 4.5 7.1 9.0

  11. Performance

  12. Summary • 3D integration • can improve memory bandwidth • makes it possible to reduce the cache miss penalty • SC-VLS cache • can dynamically change the line sizes • reduces the energy consumption up to 75%

  13. THANK YOU ACKNOWLEDGEMENT This research was supported in part by New Energy and Industrial Technology Development Organization

  14. Architecture

  15. Adequate Line Size Analysis • We execute cache simulation with each line size independently to determine an adequate line size • An average cache miss rate of each function is calculated • We compare the average cache miss rates with all line size candidates • A line size which the cache miss rate is the smallest is determined as an adequate line size

  16. Energy Model Total energy of $L1 Total energy of stacked DRAM # L1 memory access # main memory access average energy for a cache access average energy for a cache access # activated DRAM sub-array

  17. Average SC-VLS Cache Line Size

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