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آرایه های دروازه ای قابل برنامه ریزی میدانی Field Programmable Gate Arrays (FPGAs) PowerPoint PPT Presentation


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مباحث ویژه در الکترونیک. آرایه های دروازه ای قابل برنامه ریزی میدانی Field Programmable Gate Arrays (FPGAs). مدرس : دکتر محمدرضا مسلمی [email protected] مقدمه. ASIC چیست؟. مخفف کلمات Application Specific Integrated IC است.

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آرایه های دروازه ای قابل برنامه ریزی میدانی Field Programmable Gate Arrays (FPGAs)

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Field Programmable Gate Arrays (FPGAs)

:

[email protected]


ASIC

  • Application Specific Integrated IC.

  • .

  • - (RAM) (ROM) .

  • .

  • .

  • .


  • .

  • .

.


FPGA

  • Field Programmable Gate Array.

  • .

  • - .

  • FPGA .

  • .

  • .


  • .

  • .

  • .

  • FPGA .

  • ASIC .

:

-


FPGA :

Xilinx, Altera, Lattice, Actel

FPGA


(Xilinx)

1984 .

2600 .

FPGA .

IBM UMC Seiko .

:

ISI, Fandation

(Altera)

1983 .

1992 (Look Up Table) .

FPGA .

TSMC .

:

Quartus II, Max Plus II


FPGA

FPGA

(Truth table) .

.

4 1 .

RAM 4 1 .

RAM 16 16 .

RAM .

.


RAM FPGA .

.

PROM FPGA .

RAM . .

FPGA .

  • PROM (Anti fuse)

  • EEPROM

  • FLASH

  • RAM

FPGA ( )

LUT (Look Up Table)

.


3


FPGA

(Sequential) FPGA .

FPGA LUT .

MUX .

(Logic Cell) Slice

FPGA

Xilinx:LC Logic Cell

Altera:LE Logic Element


Slice .

2 Slice

Configurable Logic Block (CLB)

.

Slice 0

CLB FPGA .

LUT

PRE

Carry

D

Q

CE

CLR

Stratix II Altera

ALM (Adaptive Logic Module)

.

LUT

Carry

PRE

D

Q

CE

Slice LC .

CLR

Slice 4 .

2 2



FPGA


FPGA CLB .

RAM LUT .

CLB .

2 4096 .

2


Xilix, Altera .

18 .

.

Xilix, Altera Virtex-II Pro .

FPGA .

PowerPC IBM FPGA .


FPGA

  • .

  • .

  • .

  • .

  • HDL Designer (HDS) .

  • .


FPGA :

VHDL, Verilog

(Cuncurrent) . (()) (()) .

VHDL: Very High Speed Description Language

VHDL .vhd .

VHDL (entity) .


  • .

  • .

  • FPGA .

  • VHDL Verilog :

  • ModelSim Model Technology

  • LDV Cadence


.

test fixture ( Verilog) test bench ( VHDL) .

.

test bench .


(Synthesis) .

HDL .

FPGA Express, FPGA Compiler II, Leonardo Spectrum, Simplify .

FPGA .

4 .


Translation: .

Mapping: FPGA LUT ... .

Placement: .

Routing: . FPGA routing .

.

Quartus II Xilinx ISE Design .


VHDL

VHDL .

1- (Library Decleration): .

2- (Entity): () .

3- (Architectue): .

.

VHDL 3 (Package) 3 .


  • std_logic_1164 ieee

  • standard std

  • work work

:

LIBRARY library_name;

Use library_name.package_name.package_parts;

LIBRARY ieee;

Use ieee.std_logic_1164.all;

LIBRARY std;

Use std.standard.all;

VHDL .


(Entity)

  • .

  • ENTITY entity_name IS

  • PORT (

  • port_name: signal_modesignal_type;

  • port_name: signal_modesignal_type;

  • );

  • END entity_name;

mode .

In, out, inout, buffer

.


type .

Bit, integer, std_logic

(Architecture)

  • .

  • 1- ( ): .

  • 2- .

  • ARCHITECTURE architecture_name of entity_name IS

  • [Decleration]

  • BEGIN

  • (code)

  • END architecture_name;


: NAND

ENTITY nand_gate IS

PORT (a, b: IN BIT;-- inputs

x: OUT BIT);-- outputs

END nand_gate;

ARCHITECTURE my_arch of nand_gate IS

Signal int: std_logic;-- internal signal decleration

BEGIN

int <= a and b;

x <= NOT int;

END my_arch ;

ENTITY nand_gate IS

PORT (a, b: IN BIT;

x: OUT BIT);

END nand_gate;

ARCHITECTURE my_arch of nand_gate IS

BEGIN

x <= a NAND b;

END my_arch ;

int NAND .

VHDL .

NOT, AND, NAND, OR, NOR, XOR, XNOR


:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Half_adder_mine is

Port ( X : in STD_LOGIC;

Y : in STD_LOGIC;

S : out STD_LOGIC;

C : out STD_LOGIC);

end Half_adder_mine;

architecture Behavioral of Half_adder_mine is

begin

S <= X xorY;

C <= X and Y;

end Behavioral;


library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Three_input_gates is

Port ( IN0, IN1, IN2 : in STD_LOGIC;

OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 : out STD_LOGIC);

end Three_input_gates;

architecture Behavioral of Three_input_gates is

begin

OUT0 <= IN0 and IN1 and IN2;

OUT1 <= IN0 or IN1 or IN2;

OUT2 <= not (IN0 and IN1 and IN2);

OUT3 <= not (IN0 or IN1 or IN2);

OUT4 <= IN0 xor IN1 xor IN2;

OUT5 <= IN0 xnor IN1 xnor IN2;

end Behavioral;


BIT, BIT_VERCTOR

STD_LOGIC, STD_LOGIC_VECTOR

STD_ULOGIC, STD_ULOGIC_VECTRO

BOOLEAN

INTEGER

NATURAL

REAL

SIGNED, UNSIGNED

INTEGER

ENUMERATED


IEEE1076 IEEE1164 .


BIT BIT_VECTOR ( 0 1 )


STD_LOGIC STD_LOGIC_VECTOR

  • 8 ieee1164 .

  • 0, 1, Z .

  • .


STD_ULOGIC STD_ULOGIC_VECTOR

  • 9 .

  • U (Unresolved) .

  • . .


Boolean: TRUE FALSE .

INTEGER: 2147483647- 2147483647 .

NATURAL: 0 2147483647 .

REAL: -1.0E38 1.0E38 . ( .


: .

INTEGER

ENUMERATED


TYPE type_name IS ARRAY (specification) OF data_type;

SIGNAL signal_name: type_name [:=initial_value];

: 1D*1D

TYPE row IS ARRAY (7 downto 0) OF std_logic;-- 1D Array

TYPE matrix IS ARRAY (0 to 3) OF row;-- 1D * 1D

SIGNAL x: matrix;

: 2D

TYPE matrix2D IS ARRAY (0 to 3, 7 downto 0) of std_logic;-- 2D Array

: & .

  • ARCHITECTURE rtl OF exIS

  • SIGNAL a:std_logic_vetor (5 DOWNTO 0);

  • SIGNAL b, c, d : std_logic_vector(2 DOWNTO 0);

  • BEGIN

    • B <= 0 & c(1) & d(2);

  • END generic_decoder;

If c = 011, d = 101 ===> B = 011

IF c & d = 001100 THEN


VHDL WORK .

. .

std, work .

.

... .

.

.

(Package)

  • (Package) function procedure .

  • .


.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

----------------------------------------------------------------------------

PACKAGE my_data_types IS

TYPE vector_array IS ARRAY (natural range <>) of std_logic_vector (7 downto 0);

END my_data_types;

----------------------------------------------------------------------------

.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.my_data_types.all; -- User-defined package

----------------------------------------------------------------------------

entity MUX is

port(I:invector_array (3 downto 0); S vector_array (1 downto 0); Y: out bit);

end MUX;


function procedure .

.

PACKAGE my_packIS

FUNCTION minimum (a, b: IN std_logic_vector)

RETURN std_logic_vector;

CONSTANT max_int: integer := 16#FFFF#;

TYPE arithmetic_mode_typeIS (signed, unsigned)

END my_pack;

--------------------------------------------------------------------------------

PACKAGE BODY my_packIS

FUNCTION minimum (a, b: IN std_logic_vector)

RETURN std_logic_vector;

BEGIN

IF a < b THEN

RETURN a;

ELSE

RETURN b;

END IF;

END minimum;

END my_pack;


.

1- => .

2- =: .

3- <= OTHERS .


BIT STD_LOGIC STD_ULOGIC .

:

NOT, AND, OR, NAND, NOR, XOR, XNOR

:

Y <= NOT a AND b; -- (a.b)

Y <= NOT(a AND b); -- (a.b)

Y <= a NAND b;-- (a.b)

INTEGER SIGNED UNSIGNED REAL .

:

+ (), - (), * (), / (), ** (),

MOD ( ), REM (), ABS ()


.

:

= (), /= (), < (), > (), <= ( ), >= ( )

.

sll: .

srl: .

ARCHITECTURE rtlOF ex3IS

BEGIN

BEGIN

q1 <= 0;

q2 <= 0;

q3 <= 0;

END rtl;

ARCHITECTURE rtl2 OF ex3IS

BEGIN

BEGIN

q1 <= 001;

q2 <= 010;

q3 <= 111;

END rtl;


VHDL


IF

IF .

ENTITY ex_ifIS

PORT (a, b : IN INTEGER;

c : OUTBOOLEAN);

END;

ARCHITECTURE rtlOF ex_ifIS

BEGIN

PROCESS (a,b)

BEGIN

IF a > b THEN

c <= TRUE;

ELSE

c <= FALSE;

END IF;

END PROCESS;

END rtl;

IF SEL = 0 THEN

C <= A;

ELSE

C <= B;

END IF;


VHDL .

VHDL .

ARCHITECTURE example of ex IS

BEGIN

a <= b;

b <= c;

END my_arch ;

ARCHITECTURE example of ex IS

BEGIN

b <= c;

a <= b;

END my_arch ;

c C .

WHEN

ENTITY ex IS

PORT (a, b, c: IN std_logic;

data: IN std_logic_vector (1 downto 0);

q: OUT std_logic);

END ex;

-----------------------------------

ARCHITECTURE rtl OF ex IS

BEGIN

q <= a WHEN data = "00" else

b WHEN data = "11" else

c;

END rtl;

a

ex

b

c

q

Data [1 0]


library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Compare_mine is

Port ( A : in STD_LOGIC_VECTOR (3 downto 0);

B : in STD_LOGIC_VECTOR (3 downto 0);

Y0 : out STD_LOGIC;

Y1 : out STD_LOGIC;

Y2 : out STD_LOGIC;

Y3 : out STD_LOGIC;

Y4 : out STD_LOGIC;

Y5 : out STD_LOGIC);

end Compare_mine;

architecture Behavioral of Compare_mine is

begin

Y0 <= '1' when A = B else '0';

Y1 <= '1' when A /= B else '0';

Y2 <= '1' when A < B else '0';

Y3 <= '1' when A <= B else '0';

Y4 <= '1' when A > B else '0';

Y5 <= '1' when A >= B else '0';

end Behavioral;


3*8

architecture Behavioral of Decoder3_8_mine is

begin

Y <= "00000001" when D = "000" else

"00000010" when D = "001" else

"00000100" when D = "010" else

"00001000" when D = "011" else

"00010000" when D = "100" else

"00100000" when D = "101" else

"01000000" when D = "110" else

"10000000" when D = "111" else

"00000000" ;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Decoder3_8_mine is

Port ( D : in STD_LOGIC_VECTOR (2 downto 0);

Y : out STD_LOGIC_VECTOR (7 downto 0));

end Decoder3_8_mine;


1*8

architecture Behavioral of MUX81_mine is

begin

Y <= D(0) when A = "000" else

D(1) when A = "001" else

D(2) when A = "010" else

D(3) when A = "011" else

D(4) when A = "100" else

D(5) when A = "101" else

D(6) when A = "110" else

D(7) when A = "111" else

'Z' ;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity MUX81_mine is

Port ( D : in STD_LOGIC_VECTOR (7 downto 0);

A : in STD_LOGIC_VECTOR (2 downto 0);

Y : out STD_LOGIC);

end MUX81_mine;


WITH

WHEN ELSE WITH .

WITH .

ENTITY ex IS

PORT (a, b, c: IN std_logic;

data: IN std_logic;

q: OUT std_logic);

END ex;

-----------------------------------

ARCHITECTURE rtl OF ex IS

BEGIN

WITH data SELECT

q <= a WHEN "00,

b WHEN "11,

c WHEN OTHERS;

END rtl;


ENTITY case_muxIS

PORT (a, b, sel : IN BIT;

c : OUTBIT);

END;

ARCHITECTURE rtlOF case_muxIS

BEGIN

case selIS

WHEN 0 => c <= a;

WHEN 1 => c <= b;

END case;

END rtl;

CASE

.

ENTITY case_ex2 IS

PORT (a : IN INTEGER RANGE 0 to 30;

c : OUTINTEGER RANGE 0 to 6);

END;

ARCHITECTURE rtlOF ex_case2 IS

BEGIN

case a IS

WHEN 0 => b <= 3;

WHEN 1 | 2 => b <= 2;

WHEN OTHERS => b <= 0;

END case;

END rtl;

case . OTHERS .


FOR LOOP (WHILE LOOP)

ENTITY ex IS

PORT (a, b, c: IN std_logic_vector (4downto0);

q : OUT std_logic_vector (4downto0));

END ex;

ARCHITECTURE rtlOF ex IS

BEGIN

for I in 0 to 4 LOOP -- (WHILE I <= 4 LOOP)

IF a(i) = 1 THEN

q(i) <= b(i);

ELSE

q(i) <= c(i);

END IF;

END LOOP;

END;

Generate For .

OK: For I In Range 0 to 7 GENERATE

output(i) <= 1 WHEN (a(i) AND b(i))=1 ELSE 0;

END GENERATE;

.


:

dLOW: .

dHIGH: .

dLEFT: .

dRIGHT: .

dLENGTH: .

dRANGE: .

dREVERSE_RANGE: .


: . ( )

sEVENT: s ( ) 1 .

sSTABLE: s ( ) 1 .

sACTIVE: s = 1 .

sLAST_EVENT: s .

sLAST_ACTIVE: s = 1 .

sLAST_VALUE: s .


.

( )

C <= 1,

0 AFTER 10 ns,

b AFTER 20 ns;

VHDL

. ( )

.

b1 <= a AFTER 10 ns;

b2 < a TRANSPORT AFTER 10 ns;

B

A

A

B1

10

20

30

40

50

60

ns

B2


  • Waiting

(Process)

.

WAIT WAIT

. : wait until clk = 1

.

.

.

Sync_process: PROCESS

BEGIN

WAIT UNTIL clk = 0;

c_out <= NOT (a_inANDb_in);

d_out <= NOT b_inAFTER 10 ns;

END PROCESS sync_process;


VHDL .

1-

2- ()

( (( <= )) if/case ) .

Sync_process: PROCESS (a_in, b_in)

BEGIN

c_out <= NOT (a_inANDb_in);

d_out <= NOT b_inAFTER 10 ns;

END PROCESS sync_process;

.

a_in c_out b_in .


()

.

example: PROCESS

BEGIN

WAIT UNTIL clk = 1;

d_out <= d_in;

END PROCESS example;

.

PROCESS

BEGIN

WAIT UNTIL clk = 1;

IF en = 1 THEN

q <= d;

END IF;

END PROCESS;


wait

.

Process (a,b)

Wait until a=1;

Wait on a,b;

Wait for 10 ns;

wait on a,b .

PROCESS (a)

BEGIN

c1 <= NOT a;

END PROCESS;

PROCESS

BEGIN

c2 <= NOT a;

WAIT ON a;

END PROCESS;

PROCESS

BEGIN

WAIT UNTIL a = 1;

c4 <= NOT a;

END PROCESS;

PROCESS

BEGIN

c5 <= NOT a;

WAIT UNTIL a = 1 FOR 10 ns;

END PROCESS;


--------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

--------------------------------------------

ENTITY dff IS

port(d, clk, rst: IN STD_LOGIC;

q: OUT STD_LOGIC);

END dff;

--------------------------------------------

ARCHITECTURE behavior OF dff IS

BEGIN

sve: PROCESS(rst,clk)

BEGIN

IF (rst='1') THEN

q <= '0';

ELSIF (clk'EVENT AND clk='1') THEN

q <= d;

END IF;

END PROCESS sve;

END behavior;

--------------------------------------------

: DFF


ENTITY example IS

PORT (a, b, clk : IN BIT;

q: OUT BIT);

END example ;

ARCHITECTURE example of example IS

SIGNAL temp : BIT;

BEGIN

temp <= a nand b;

PROCESS (clk)

BEGIN

IF (clk EVENT and clk = 1) then q <= temp;

END IF;

END PROCESS;

END example ;

: DFF NAND

.

AFTER .

ARCHITECTURE my_arch of nand_gate IS

BEGIN

x <= a NAND b AFTER 10 ns; -- Component Delay = 10 ns

END my_arch ;


Multiplexer

WHEN ELSE WITH .

WITH .

ENTITY mux2 IS

PORT (sel_0, a, b: IN std_logic;

q: OUT std_logic);

END mux2;

-----------------------------------

ARCHITECTURE mux2_with OF mux2 IS

BEGIN

WITH sel_0 SELECT

c <= a AFTER 10 ns WHEN 0,

b AFTER 10 ns WHEN OTHERS;

END mux2_with;

(generic)

ENTITY nand_gateIS

GENERIC (delay: time:=10ns);

PORT (a, b: IN BIT;

x: OUT BIT);

END nand_gate;

ARCHITECTURE my_arch of nand_gate IS

BEGIN

x <= a NAND b AFTER delay;

END my_arch ;

.

.


LIBRARY ieee;

USE ieee.std_logic_1164.all;

--------------------------------------------------------

ENTITY decoder IS

PORT( ena : IN std_logic;

sel : IN std_logic_vector (2 downto 0);

x : OUT std_logic_vector (7 downto 0));

END decoder;

--------------------------------------------------------

ARCHITECTURE generic_decoder OF decoder IS

BEGIN

PROCESS (ena, sel)

VARIABLE temp1: std_logic_vector (x'HIGHdownto 0);

VARIABLE temp2: integer RANGE 0 to x'HIGH;

BEGIN

temp1 := (OTHERS => '1');

temp2 := 0;

IF (ena='1') then

FOR i in sel'RANGE LOOP -- sel range is 2 downto 0

IF (sel(i)='1') THEN-- bin to integer conversion

temp2 := 2*temp2+1;

ELSE

temp2 := 2*temp2;

END IF;

END LOOP;

temp1(temp2) := '0';

END IF;

x <= temp1;

END Process;

END generic_decoder;

:


LIBRARY ieee;

USE ieee.std_logic_1164.all;

--------------------------------------------------------

GENERIC ( bits : INTEGER := 8;

words : INTEGER := 16);

ENTITY ram IS

PORT( wr_ena, clk: IN std_logic;

addr: IN INTEGER RANGE 0 to words-1;

data_in: IN std_logic_vector(bits-1 downto 0));

data_out: OUT std_logic_vector(bits-1 downto 0));

END ram;

--------------------------------------------------------

ARCHITECTURE ram OF ram IS

TYPE vector_array IS ARRAY (0 TO words-1) OF std_logic_vector (bits-1downto0);

SIGNAL memory: vector_array;

BEGIN

PROCESS (clk, wr_ena)

BEGIN

IF (wr_ena='1') then

IF (clkEVENT AND clk = 1) THENmemory(addr) <= data_in;

END IF;

ELSEIF (wr_ena=0') then

IF (clkEVENT AND clk = 1) THENdata_out<= memory(addr);

END IF;

END IF;

END Process;

END ram;

: RAM


.

.

.

. 3 .

Comparator

A

B

A>B

A=B

A<B

>

=

<


NAND .

.

.

inv

o1

i1

Buffer port

Entity name

Output port

Bidirectional

port

Input port


VHDL

ENTITY inv IS

PORT ( I1 : IN BIT; O1 : OUT BIT);

END inv;

ARCHTECTURE single_delay OF inv IS

BEGIN

o1 <= NOT I1 AFTER 4 ns;

END single_delay;

TIME 1 (15-10) .

NAND

VHDL

ENTITY nand2 IS

PORT ( I1, I2 : IN BIT; O1 : OUT BIT);

END inv;

ARCHTECTURE single_delay OF nand2 IS

BEGIN

o1 <= I1 nand I2 AFTER 5 ns;

END single_delay;

nand2

i1

o1

i2


NAND

VHDL

ENTITY nand3 IS

PORT ( I1, I2 : IN BIT; O1 : OUT BIT);

END inv;

ARCHTECTURE single_delay OF nand3 IS

BEGIN

o1 <= NOT (I1 and I2 and I3) AFTER 5 ns;

END single_delay;

nand3

i1

o1

i2

i3

VHDL .

.


.

A>B A B A B > .

A=B A B = .

A<B .

.

a_gt_b = a.gt + b.gt + a.b

a_eq_b = a.b.eq + a.b.eq

a_lt_b = a.lt + b.lt + a.b


a

  • .

  • .

a_gt_b

b

gt

a_eq_b

nand3

nand3

nand3

nand3

eq

Bit_comparator

i1

i1

i1

i1

inv

inv

o1

o1

i1

i1

o1

o1

o1

o1

i2

i2

i2

i2

lt

i3

i3

i3

i3

a

b

a_gt_b

gt

a_lt_b

a_eq_b

eq

a_lt_b

lt

nand2

nand2

nand2

nand2

nand2

nand2

nand2

i1

i1

i1

i1

i1

i1

i1

o1

o1

o1

o1

o1

o1

o1

i2

i2

i2

i2

i2

i2

i2


ENTITY bit_comparator IS

PORt ( a, b,

gt,

eq,

lt : IN BIT;

a_gt_b,

a_eq_b,

a_lt_b : OUT BIT);

END bit_comparator

ARCHITECTURE gate_level OF bit_comparator IS

COMPONENT n1 PORT (i1 : IN BIT; o1 : OUT BIT); END COMPONENT;

COMPONENT n2 PORT (i1 , i2 : IN BIT; o1 : OUT BIT); END COMPONENT;

COMPONENT n3 PORT (i1 , i2 , i3 : IN BIT; o1 : OUT BIT); END COMPONENT;

FOR ALL: n1 USE ENTITY WORK.inv (single_delay);

FOR ALL: n2 USE ENTITY WORK.nand2 (single_delay);

FOR ALL: n3 USE ENTITY WORK.nand3 (single_delay);

-- Intermediate signals

SIGNAL im1, im2, im3, im4, im5, im6, im7, im8, im9, im10: BIT;

BEGIN

-- a_gt_b output

G0: n1 PORT Map (a, im1);

G1: n1 PORT Map (b, im2);

G2: n2 PORT Map (a, im2, im3);

G3: n2 PORT Map (a, gt, im4);

G4: n2 PORT Map (im2, gt, im5);

G5: n3 PORT Map (im3, im4, im5, a_gt_b);


-- a_eq_b output

G6: n3 PORT Map (im1, im2, eq, im6);

G7: n3 PORT Map (a, b, eq, im7);

G8: n2 PORT Map (im6, im7, a_eq_b);

-- a_lt_b

G9: n2 PORT Map (im1, b, im8);

G10: n2 PORT Map (im1, lt, im9);

G11: n2 PORT Map (b, lt, im10);

G12: n3 PORT Map (im8, im9, im10, a_lt_b);

END gate_level;

.

( ) .

VHDL .

MAP .


Test Bench

VHDL FPGA .

.

.

. ModelSim .

:

.

.


:

.

.

.

In_model <= 1 AFTER 5 ns,

0 AFTER 100 ns,

1 AFTER 200 ns,

0 AFTER 300 ns + 4 ns;

Clk <= NOT clk AFTER 50 ns;

1:

clk 50 .

std_logic .

VHDL .

Bit std_logic U . .

SIGNAL clk: STD_LOGIC := 0


In_vect <= 00 AFTER 5 ns,

01 AFTER 100 ns,

10 AFTER 200 ns,

11 AFTER 300 ns + 4 ns;

PROCESS

BEGIN

in_s1 <= 1;

in_s2 <= 0;

WAIT UNTIL reset = 1;

WAIT UNTIL clk= 1;

in_s1 <= 0;

in_s2 <= 1;

wait .

. Clk.

.

CONSTANT period : TIME := 50 ns;

WAIT FOR period;

WAIT FOR 2 * period;


.

. .

.

2 .

3 .

Test_My_comp

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY test_my_comp IS

PORT (d_out, en, overflow : OUT std_logic;

q: OUT std_logic_vector (2 DOWNTO 0));

END;

ARCHITECTURE testbench OF test_my_comp IS

COMPONENT my_comp

PORT (clk, resetn, d_in : IN std_logic;

a, b: IN std_logic_vector (2 DOENTO 0);

d_out, en:OUT std_logic;

overflow:OUT std_logic;

q:OUT std_logic_vector(2 DOWNTO 0);

END component;

My_comp

clk

D_out

resetn

en

D_in

overflow

a

q

b


SIGNAL clk: std_logic:= 0;

SIGNAL resetn: std_logic:= 0;

SIGNAL d_in: std_logic:= 0;

SIGNAL a, b: std_logic_vector (2 DOENTO 0);

FOR U1: my_comp USE ENTITY work.my_comp (rtl);

BEGIN

U1: my_comp PORT MAP (clk, resetn, d_in, a, b, d_out, en, overflow, q);

clk <= NOT clk AFTER 50 ns;

resetn <= 1 AFTER 125 ns;

a <= 000,

010 AFTER 125 ns,

100 AFTER 175 ns;

b <= 000,

100 AFTER 125 ns,

011 AFTER 175 ns;

PROCESS

BEGIN

d_in <= 0;

WAIT UNTIL resetn = 1;

d_in <= 1;

WAIT UNTIL clk = 1;

d_in <= 0 AFTER 10 ns;

WAIT;

END PROCESS;

END;


1: 4 . .

2: 8 3 . .

3: 4 .

4: BCD . 1 4 . .


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