C ombinationality checking of cyclic circuits
This presentation is the property of its rightful owner.
Sponsored Links
1 / 30

C ombinationality checking of cyclic circuits PowerPoint PPT Presentation


  • 52 Views
  • Uploaded on
  • Presentation posted in: General

C ombinationality checking of cyclic circuits. Wan-Chen Weng Date: 2013/12/30. Outline. Motivation Problem formulation Combinationality Methodology Outer and Inner Side Input Loop back tracing Program flow Future work. Motivation (1/4). S. Malik (1994)

Download Presentation

C ombinationality checking of cyclic circuits

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


C ombinationality checking of cyclic circuits

Combinationality checking of cyclic circuits

Wan-Chen Weng

Date: 2013/12/30


Outline

Outline

  • Motivation

  • Problem formulation

  • Combinationality

  • Methodology

    • Outer and Inner Side Input

    • Loop back tracing

  • Program flow

  • Future work


Motivation 1 4

Motivation(1/4)

  • S. Malik (1994)

    • For the analysis of cyclic circuits.

    • Let  denote the unknown value.


Motivation 2 4

Motivation(2/4)

  • Marc D. Riedel (2008)

    • SAT-based dual-rail model checking for the combinationality of cyclic circuits.

    • Add dummy variables and equivalent checkers to the corresponding module.


Motivation 3 4

Motivation(3/4)

  • Marc D. Riedel (2008)

    • The original circuit will be combinational when SAT = 0.


Motivation 4 4

Motivation(4/4)

  • Dual-rail model

    • checks the combinationality of cyclic circuits in a more elegant way.

    • still consumes memories and is the bottleneck when the circuit size is large.


Combinationality 1 4

Combinationality(1/4)

  • Stephen A. Edwards (2003)

    • for a circuit with a strongly-connected component (SCC) to behave combinationally, at least one input to a gate in the SCC must be driven to a controlling value.


Combinationality 2 4

Combinationality(2/4)

  • J.-H. R. Jiang (2004)

    • Functional-level analysis is not sufficient to conclude the correctness of the gate-level implementation.


Combinationality 3 4

Combinationality(3/4)

  • Function level

    • For any input assignment, the output valuates to the same fixed value after a bounded amount of time.

  • Circuit level

    • Depending on timing and circuit model.


Combinationality 4 4

Combinationality(4/4)

SAT

non-combinational

(SAT)

SAT

SAT

combinational

(UNSAT)

UNSAT

UNSAT

combinational

(UNSAT)

SAT


Problem formulation 1 1

Problem formulation(1/1)

  • Given:

    • a cyclic circuit C.

  • Determine:

    • if C is combinational.

  • By using:

    • SAT-based approaches describing relations between nodes in SCCs and SCCs’ fanout cones.

  • If:

    • SAT-solver returns UNSAT, Ccannot output  andis combinational.


Outer and inner side input 1 7

Outer and Inner Side Input (1/7)

For

everyinputassignment

If

(A,B,C)=(CV,CV,CV)

Then

everyfanoutisanexactvalue.

Thus

loopsarefalseandtheSCCiscombinational.

n1

A

BUT!

It’stoostrictfor(A,B,C)tobe(CV,CV,CV)ineveryassignment.

n4

n2

B

n3

C


Outer and inner side input 2 7

Outer and Inner Side Input (2/7)

For

aninputassignment

If there exist a set of

(A,B,C)that can break all loops in the SCC

Then

the SCC is still combinational.

n1

A

For example:

(A, B, C) = (NCV, CV, NCV) or

(A, B, C) = (CV, NCV, CV) is fine.

n4

n2

B

n3

C


Outer and inner side input 3 7

Outer and Inner Side Input (3/7)

n1

A

n4

n2

B

n3

C

  • Outer side input(OSI) vs. Inner side input(ISI)

    • OSIs:areside inputs entirely from somewhere outside the SCC.

    • ISIs: are side inputs from somewhere inside the SCC.

  • OSIs:

  • ISIs:


Outer and inner side input 4 7

Outer and Inner Side Input (4/7)

n1

A

n4

n2

B

n3

C

  • Outer side input(OSI) vs. Inner side input(ISI)

    • OSIs:areside inputs entirely from somewhere outside the SCC.

    • ISIs: are side inputs from somewhere inside the SCC.

  • OSIs: A, B, C

  • ISIs:


Outer and inner side input 5 7

Outer and Inner Side Input (5/7)

n1

A

n4

n2

B

n3

C

  • Outer side input(OSI) vs. Inner side input(ISI)

    • OSIs:areside inputs entirely from somewhere outside the SCC.

    • ISIs: are side inputs from somewhere inside the SCC.

  • OSIs: A, B, C

  • ISIs:

    • n3 (for loopn2_n1_n4)


Outer and inner side input 6 7

Outer and Inner Side Input (6/7)

n1

A

n4

n2

B

n3

C

  • Outer side input(OSI) vs. Inner side input(ISI)

    • OSIs:areside inputs entirely from somewhere outside the SCC.

    • ISIs: are side inputs from somewhere inside the SCC.

  • OSIs: A, B, C

  • ISIs:

    • n3 (for loopn2_n1_n4)

    • n1 (for loopn2_n3_n4)


Outer and inner side input 7 7

Outer and Inner Side Input (7/7)

  • (OSIx_1∧ … ∧OSIx_n∧ ISIx_1∧ … ∧ISIx_n)

  • = (NCV ∧ … ∧NCV ∧NCV ∧ … ∧NCV)

  • (loopy_1∨ …∨loopy_x∨ … ∨ loopy_n) = SAT

  • For a loopx:

    • If

    • Then loopx is not combinational. (a true loop)

  • For an SCCy:

    • If

    • Then the SCC is not combinational.


Loop back tracing 1 9

Loop back tracing (1/9)

Clause of the loop (OSIs/ISIs):

(A ∧ B)

Clause of n1, n2:

n1 = A‧n2

(A∨n2∨n1)∧ (A∨n1) ∧ (n2∨n1)

n2 = B‧n1

(B∨n1∨n2)∧ (B∨n2) ∧ (n1∨n2)

Results: [SAT]

(n1, n2) = (0, 0) or (1, 1)

n2

A

B

n1


Loop back tracing 2 9

Loop back tracing (2/9)

Clause of the loop (OSIs/ISIs):

(A ∧ B)

Clause of n1, n2:

n1 = A‧n2

(A∨n2∨n1)∧ (A∨n1) ∧ (n2∨n1)

n2 = B‧n1

(B∨n1∨n2)∧ (B∨n2) ∧ (n1∨n2)

Results: [UNSAT]

n2

A

B

n1


Loop back tracing 3 9

Loop back tracing (3/9)

In fact:

if

(A, B) = (NCV, NCV)

then

(n1, n2) = (1/0, 0/1) or

(n1, n2) = (0/1, 1/0).

Which means:

n1 and n2 always toggletheir value in the same input assignment.

n2

A

B

n1


Loop back tracing 4 9

Loop back tracing (4/9)

  • The weakness of SAT solvers

    • No timing concept.

    • Cannot detect UNKNOWN happened across time frames.

    • Can only distinguish the uncertainty but oscillation.

  • Notation

    • Time frame: T.


Loop back tracing 5 9

Loop back tracing (5/9)

nT-1

nT

To represent the value of a node in T and T-1, we derive an equation with its fanins and trace back the fanin cone until the node be reached again as well as all variables in the equation are not in time T.


Loop back tracing 6 9

Loop back tracing (6/9)

n3T

= C‧n2T = C‧ (B‧n4T)

=C‧B‧ (n3T-1‧n1T)

=C‧B‧n3T-1‧(A‧n2T-1)

=A‧B‧C‧n3T-1‧n2T-1

n1

A

n1T

= A‧n2T = A‧ (B‧n4T)

=A‧B‧ (n1T-1‧n3T)

=A‧B‧n1T-1‧(C‧n2T-1)

=A‧B‧C‧n1T-1‧n2T-1

n4

n2

B

(B ∧ A ∧ n3) ∨ (B ∧ C ∧ n1)

n3

C

  • E.g.,


Loop back tracing 7 9

Loop back tracing (7/9)

n3T =A‧B‧C‧n3T-1‧n2T-1

e.g.

P=A‧B‧C‧Q‧R

n1

A

n1T =A‧B‧C‧n1T-1‧n2T-1

e.g.

W=A‧B‧C‧Y‧R

n4

n2

B

n3

C

To distinguish the value of a node in T and T-1, assign nodeT and nodeT-1 to different variables.


Loop back tracing 8 9

Loop back tracing (8/9)

n1

n1

A

A

n3T =A‧B‧C‧n3T-1‧n2T-1

n1T =A‧B‧C‧n1T-1‧n2T-1

(A,B,C,n1T,n1T-1,n2T-1,n3T,n3T-1)

=(1,1,1,1,1,1,1)or(1,1,1,0,0,0,0)

n3T =C+B+n3T-1+A‧n2T-1

n1T =A+B+n1T-1+C‧n2T-1

(A,B,C,n1T,n1T-1,n2T-1,n3T,n3T-1)

=(1, 1, 1, 0, 1, 1, 0, 1)

n4

n4

n2

n2

B

B

n3

n3

C

C

  • Can detectoscillation and uncertainty.


Loop back tracing 9 9

Loop back tracing (9/9)

n1T= A‧n2T = A‧(B‧n4T)

= A‧B‧(n1T-1‧n3T)

= A‧B‧n1T-1‧(C‧n2T-1)

= A‧B‧C‧n2T-1‧n1T-1

n2T = B‧n4T = B‧(n1T‧n3T)

= B‧(A‧n2T-1)(C‧n2T-2)

= A‧B‧C‧n2T-1‧n2T-2

n3T=A‧B‧C‧n2T-1‧ n3T-1

n4T = A‧B‧C‧n2T-1‧n4T-1

n1

A

n4

n2

B

nkT = OSI1‧…‧OSIx‧

n1T-(#fanout-1)‧n1T-(#fanout-2)‧…‧n2T-(#fanout-1)‧…‧

nkT-(#fanout)

n3

C

  • Boolean equations:


Program flow 1 1

Program flow (1/1)

Cyclic circuit C

Find an SCC S

Find a loop L in S

SAT solving

Derive the back tracing equation BTE of an ISIof L

SAT

SAT?

UNSAT

Transform BTE into the CNF

YES

Exists unfinished SCC?

YES

Exists unfinished ISI?

NO

NO

YES

Exists unfinished loop?

termination

NO


Future work 1 2

Future work (1/2)

How to define the characteristic function to check whether SCCs’ fanout cone propagates  or not.

Happy New Year~~!!


Future work 2 2

Future work (2/2)

Happy New Year~~!!


  • Login