Digital System Design. Lecture # 01. Who am I?. Engr. Naveed Khan Baloch Lecturer CPED, UET Taxila Office hours: 02:30PM-03:30PM, Background: MSc Computer Engineering Research areas: Current: Processor Design, DSP Processors, FPGA
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Digital System Design
Lecture # 01
Engr. Naveed Khan Baloch
2X transistors/Chip Every 1.5 years
Called “Moore’s Law”
Gordon Moore (co-founder of Intel) predicted in 1965 that the transistor density of semiconductor chips would double roughly every 18 months.
Microprocessors have become smaller, denser, and more powerful.
Introduction to Digital design
Verilog Basics (Language Specification + Model Sim Introduction and demo)+test bench (Quiz)
Combinational Logic revision and Verilog description (Assignment)
Sequential Logic revision and Verilog description (Quiz)
Design Examples of digital designs with Verilog coding (Assignment)
FPGA Introduction, workshop on Xilinix tools, Spartan 3AN working examples Synthesis---1 (Quiz) (Assignment)
9. ASMD Introduction Traffic Light Controller + Timers (Assignment)
10. ASMD based UART , TX and RX (Quiz)
11. ASMD based 8-bit RISC processor Design Datapath and Control Unit (Assignment)
12. Addition Architectures (Quiz)
13. Multiplication Architectures (Assignment)
14. Time shared and pipelined architecture
15. Design of floating point unit / VLIW and superscalar architecture
16. DSP using Digital Design (Final)