Ariadne’s Thread

1. Ariadne’s Thread Kristian Zarb Adami

2. Simulator Aims • Provide the system architect a tool to visualise trade-offs in designs • Provide the scientist top-level performance numbers for a given system • Maintain a close relationship with the cost-model so that cost estimates can be derived from the model • Maintain a close relationship with the telescope simulation environments (eg. MeqTrees) • Provide an easy route to implementation

3. The Specificationhierarchy … Sky Line Sensitivity Continuum Sensitivity Survey Speed FoV Dynamic Range Science Dynamic Range Aeff Tsys Bandwidth Cost & Functional Model Engineering Antenna Efficiency Front-End Analog Digital Processing Signal Transport # of beams # of channels # of bits Software CORRELATION & IMAGE PIPE

4. Beam Pattern showing interference cancellation Digital Aperture Array

5. Analog One-tile sub-array antenna unit of 8x8x2 LP dipoles Processing ... 63)x2 (0 Main LN Amplifiers and WB Filters ... (0 63)x2 Digital 8x8x2 ADC Processing 2.4GS/s ... 4-bit real (0 63)x2 4-bit imag Frequency Frequency 1024x2 ... splitting splitting 8-bit preset ... ... onto 1024 onto 1024 coefficients subbands subbands 2.4MS/s ... ... 4-bit real 1023)x2 (0 (0 1023)x2 4-bit imag ... Equaliser Equaliser ... ... ... ... 1023)x2 (0 (0 1023)x2 Polarisation Polarisation ... correction correction ... ... of each H-V of each H-V pair pair ... ... ... ... ... ... 8x8x2 8x8x2 ... 2D FFT 2D FFT 0 1023 ... ... (0 63)x2 (0 63)x2 8 Beam 8 Beam ... selector selector and beam- and beam- steering steering ... ... (0 8)x2 (0 8)x2 FOV FOV ... ... correction correction ... ... (0 (0 8)x2 8)x2 2-PadSystem Example • Log-Periodic Dipole Array between 0.3 – 1GHz • Demonstrate All-Digital Aperture Array for beam-forming, calibration and RFI mitigation • Demonstrate scalability in terms of power consumption, cost and performance • Demonstrate functionality in terms of bits, bandwidth and beams

6. Analog ModelOutside Station

7. 1st filter response Channel Selection 4-bit ‘Ideal’ ADC Digitisation

8. A/D Converters • 4-bit 2.4 GS/s CMOS already available at sample level • Front-End bit-count can be increased to 8 (~50dB of Dynamic Range) for RFI mitigation, with reduced bit-count at the back-end • Equalization ‘may’ also be included in this block • Decimation and digital formatting can be integrated into back-end of A/D 2003

9. Channelization • Form channels from each ADC • Different channelisation algorithms can be tried • Equalisation can be implemented as part of the channelisation block • Data is now moved to the beamformer (windowing can occur in beamforming block)

10. ChannelizationAlgorithms

11. Cost/Power Calculationsfor 1st stage Bandwidth NOT OPS limited

12. Poly-phase filteringResponse • Side-lobes considerably reduced with increasing number of bits • Trade-off number of taps with coefficient accuracy • Aim to relate this with science goals

13. FFT Beamformer • Form many beams at once • Different beams in different directions • Windowing function can be used to suppress sidelobes (especially 13.0dB from rectangular window) • Trade-off windowing with sidelobe height and Aeff/Gain

14. 8-pt FFT • 8-pt FFT real-time model implementation • Twiddles can be retrieved from memory • Easy mapping onto FPGA/RPA interface

15. Fixed vs. Floating Point • Bit-growth per stage • 4-bit FFT vs. floating point

16. Windowingfor Sidelobe Cancellation

17. Data Memory or ADC I/O Ports x + Rate Control << Program counter Configuration stream Program Memory Reconfigurable Processor Arrays • Heterogeneous Array of Instruction cells • Rate controller to control delay in data paths • I/O Ports mapped as instruction cells • Low Power / Area • Highly Configurable • High I/O Bandwidth

18. Datapath example: Step 1 void oned_dct (int *coeff,int *block) { b0 = coeff[0]; b1 = coeff[1]; b2 = coeff[2]; b3 = coeff[3]; b4 = coeff[4]; b5 = coeff[5]; b6 = coeff[6]; b7 = coeff[7]; e = b1 * const_f7 - b7 * const_f1; f = b5 * const_f3 - b3 * const_f5; c4 = e + f; c5 = e - f; h = b7 * const_f7 + b1 * const_f1; g = b3 * const_f3 + b5 * const_f5; c6 = h - g; c7 = h + g; c0 = (b0 + b4) * const_f4; c1 = (b0 - b4) * const_f4; c2 = b2 * const_f6 - b6 * const_f2; c3 = b6 * const_f6 + b2 * const_f2; b5 = (c6 - c5) * const_f0; b6 = (c6 + c5) * const_f0; b0 = c0 + c3; b1 = c1 + c2; b2 = c1 - c2; b3 = c0 - c3; block[0] = b0 + c7; block[1] = b1 + b6; block[6] = b1 - b6; block[7] = b0 - c7; block[2] = b2 + b5; block[3] = b3 + c4; block[4] = b3 - c4; block[5] = b2 - b5; } 2 ns Step 2 1 ns Step 3 4 ns Example Code Step 4 2 ns 1 ns Step 5 Step 6 3 ns

19. Step 1 Data Memory or ADC Step 2 I/O Ports Step 3 RPA Solution - Datapath Illustration + x Rate Control Step 4 << Program counter Configuration stream Step 5 Step 6 Program Memory Off-chip bandwidth ~ 10 Gbit/s Intra-cell bandwidth ~ 100 Gbit/s

20. Future Work • Include clock delays for each block to ensure real-time data tracking (as well as JITTER !!!) • Include a calibration model for Gain/Phase calibration @ each antenna • Relate beam-forming to FoV to work out the trade-off between number of beams vs. no. of bits/ beam • Relate DSP-induced noise to noise temperature to work out contribution to Tsys • Relate side-lobe suppression models to Dynamic Range and Image Fidelity • Produce Cost / Power benchmarks for each block for input into the Cost Model • Extend model to the full-frequency coverage of a station • Produce technology and architecture roadmaps including cable architecture

21. Science Goals Technology Capabilities Simulations $$ Simulations Simulations Software Capabilities Extra slides

22. Error Modelling • Quantization error dependent on bit-width • Scaling considerations are IMPORTANT