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True Assembly Language. Part I. The Assembly Process. The process of translating a MAL code (an assembly language program) into machine code (a sequence of bits) is called assembly. The program that performs the translation is called an assembler.

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the assembly process
The Assembly Process
  • The process of translating a MAL code (an assembly language program) into machine code (a sequence of bits) is called assembly.
  • The program that performs the translation is called an assembler.
  • The translation from assembly language to machine code is mechanical, repetitive, and tedious. Small errors can have disastrous results and therefore this job is better left to computers.
Sometimes, a set of instructions are repeated several times within a code. It is best to give a name to this repetitive code sequence. A macro defines a sequence of instructions by associating to it a keyword.
  • A preprocessor can then be used to expand a macro into a series of instructions it represents.
  • Many MAL instructions are identical to TAL. The first step in assembling a MAL program is to translate the code into TAL.
tal true assembly language
TAL - True Assembly Language
  • MAL is not directly translatable into machine code because of several abstractions in the language.
  • The TAL instruction set, however, defines the MIPS RISC architecture.
  • TAL arithmetic and logical instructions generally require three-operand specifications but MAL permits two- or three-operand specifications.
arithmetic and logical instructions
Arithmetic and Logical Instructions
  • TAL has both register and immediate addressing modes, although not all have immediate modes, e.g., there is no immediate sub instruction because it can be done by add

addi Rt,Rs,I Rt [Rs]+([I15]16||I15..0)

addiu Rt,Rs,I Rt [Rs]+([I15]16||I15..0)

andi Rt,Rs,I Rt 016||([Rs]15..0 AND I15..0)

lui Rt,I Rt I15..0||016

The MAL move instruction

move Rt, Rs

is equivalent to the TAL instruction

add Rt,$0,Rs

  • Each of the MAL shift instructions exists in two forms in TAL

sll Rdest,Rsrc1,Src2

sllv Rdest,Rscr1,Rscr2

  • The first shift instruction is the same as MAL; the second one specifies a register from which the amount of shifts is obtained from. The suffix v indicate that the amount of shift is variable.
multiplication in tal
Multiplication in TAL
  • MIPS RISC architecture contains two special registers, HI and LO, that are used to hold 64-bit results.

mult Rs,Rt

takes the contents of Rs and Rt as multiplicands and places the least 32-bit result into LO and the other 32-bit result into HI.



mul $8,$9,$10

mult $9,$10

mflo $8

move from LO

HI must be checked for overflow

division in tal
Division in TAL
  • The TAL div instruction computes both the integer quotient and remainder, leaving the quotient in LO and the remainder in HI.



rem $8,$9,$10

div $9,$10

mfhi $8

div $8,$9,$10

div $9,$10

mflo $8

unsigned arithmetic
Unsigned arithmetic
  • The MIPS RISC architecture provides a set of instructions that perform unsigned arithmetic via instructions that are suffixed u.
  • These instructions never cause exceptions (error condition) even if overflow occurs. The responsibility is left to the programmer or compiler to assure that overflow never occurs when these instructions are used.

addu addiu

multu subu


branch instructions
Branch Instructions
  • Branch instructions use a signed 216 offset field, hence (because addresses must be multiples of 4, we can shift the 18 bit value right twice and just store a 16 bit value) can only jump 217-1 addresses forward and 217 backward. Jump instructions can jump longer using a 26-bit offset field.
  • Not all MAL branch instructions are available in TAL. Only bltz, blez, bgez, blez, beq, bne, and b are available.
subtle problems on branching
Subtle problems on branching



blt $11,$12,next

sub $10,$11,$12

bltz $10,next

Subtraction may cause

an overflow, e.g. if $11

contains 4000000 and

$12 contains -4000000 then

the result is 8000000 which

has no representation

slt $10,$11,$12

bne $10,$0,next

Sets $10 to 1 if the 2’s complement

of the contents of $11 is less than

the 2’s complement of the contents

of $12, else it sets $10 to 0. The

comparison does not cause overflow

load address instruction



la R, label

lui R, highaddress

ori R, lowaddress

lui $12, 0x0003

ori $12, 0x0248

la $12, 0x00030248

Load Address Instruction
  • TAL does not natively have the MAL la instruction (though la still works in TAL).

The assembler determines the address bound to

label and divides it into two halves. The upper half

is loaded into R via lui and the lower half is ored into

R using the ori instruction.