Digital System Design Course Introduction

1. Digital System DesignCourse Introduction Lecturer：　吳安宇 Date：2004/02/20

2. Contexts • Digital system design plays an important role in implementing digital functions in modern system-on-chip (SOC) design. • In this course, we will focus on developing the design skills for undergraduate students so that they can be familiar with state-of-the-art digital front-end design skills and flow. 台灣大學 吳安宇 教授

3. This course covers: • Firstly, we will introduce the Hardware Description Language (HDL). The chosen HDL is Verilog. We will formally cover • The HDL grammar • The coding guideline • The synthesis guideline • Modern cell-based synthesis flow • Reuse Manual Methodology (RMM) 台灣大學 吳安宇 教授

4. This course covers: • Secondly, we will ask students to design an advanced MIPS CPU. It is based on the knowledge of “Computer Organization and Design.” The assignment covers • Instruction development. • HDL coding and simulation of major blocks such as Arithmetic Logic Unit (ALU) and Control Unit (CU). • Enhanced CPU design with Pipelining and Forwarding • Integration of whole design. • Thirdly, port the MIPS CPU design to FPGA board and perform emulation (optional) 台灣大學 吳安宇 教授

5. Course Outline 台灣大學 吳安宇 教授

6. Verilog HDL Outlines • Overview of Verilog Hardware Describe Languages • Modeling and Verification with Verilog-HDLs • Logic Design with Behavior Models • Introduction to synthesis with Verilog-HDLs • Synthesis of Combinational Circuits • Synthesis of Sequential Circuits • State machines & Datapath Controllers • Architecture and Algorithm • Coding Style 台灣大學 吳安宇 教授

7. Advanced MIPS CPU Outlines • Overview of MIPS CPU Architecture • Instruction Sets • Arithmetic Logic Unit Design • Control Flow Design • Pipelining Architecture • Forwarding Architecture 台灣大學 吳安宇 教授

8. Course Information • Instructor: 許槐益(Huai-Yi Hsu) • E-mail: yuki@access.ee.ntu.edu.tw • Office: Rm. E2-331, New E.E. Building • Text Book • “Adanced Digital Design with the Verilog HDL.” by Michael D. Ciletti, Prentice Hall, 2003 • Reference Book • “Verilog Styles for Synthesis of Digital Systems,” by David R. Smith and Paul D. Franzon, Prentice Hall, 2001 (全華代理) 台灣大學 吳安宇 教授

9. Reference Books • M. D. Ciletti, “Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL,” Prentice-Hall, 1999. • “Verilog HDL: A Guide to Digital Design and Synthesis,” 2nd ed., by Samir Palnitkar, SunSoft, 2003 (全華代理) • “Reuse Methodology Manual for System-On-A-Chip Designs,” 3rd Edition, by Michael Keating, Pierre Bricaud, Kluwer Academic Publishers, 2002. • “Computer organization & design: The hardware/software interface,” 2nd edition, by David A. Patterson and John L. Hennessy, Morgan Kaufmann, 1998. • 黃英叡、江文啓、黃稚存、張銓淵編譯, “Verilog硬體描述語言,” 全華書局, 2001. • 楊紹聖、蕭鳴均、李進福、蔡培元編譯, “Verilog數位電腦設計,”全華書局, 2001. 台灣大學 吳安宇 教授

10. Course Grading • Participation 2% (about four times). • One mid-terms 22% • Final Projects (demo and presentation) 36% • Computer Labs and Homework (about four labs and ten homework) 40% 台灣大學 吳安宇 教授

11. Background • Programming Language, Logic Design (basic) • Computer Organization and Design (required) • VLSI Design (optional) 台灣大學 吳安宇 教授