Design of the Processor Control Unit Design. ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides7.ppt Modification date: March 27, 2014. Control Unit Control unit needs to: Generate signals for each register transfer action and other operations specified, and
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Control Unit Design
ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides7.ppt Modification date: March 27, 2014
Control unit needs to:
Generate signals for each register transfer action and other operations specified, and
Be able to sequence through the steps for fetching/ executing the instructions in the program
Pis the destination register and Q is the source register. There may be many sources and destinations. Convenient to attached all sources and destinations to a common set of wires:
Two logic signals required, one to select source, one to select destination:
Transfer takes place when destination register activated with clock.
Timing select destination:
Suppose need a sequence of steps to execute a particular instruction is:
T0: S T
T1: P Q
T2: R P
at times T0, T1, T2 ... , where S, P, and R are destinations and T, Q, and P are sources connected to the internal bus.
Strictly, the action S T is done when T0 = 1
Could use a logic circuit to generate select destination:T0, T1, T2, ...:
Example select destination:
T5: MAR PC
Usually, other conditions needed apart for a timing signal being present.
x.T5: MAR PC
Operations other than register transfer being present.
Sometimes, operations other than register transfer are specified.
R P + R
specifies an addition to be performed prior to the register transfer.
Depending upon implementation, may need to be decomposed into a series of elementary steps.
If we provide three separate buses, one for each source and one for the destination, possible to implement step in one time period - see next slide.
Processor with Three Internal Buses being present.
Control unit still has to provide necessary signals at correct times.
More complex steps - operation and data transfer being present.
Z X + Y
INSTR being present.i . Tj: Z X + Y
Similar logic circuits for each step.
Selecting source and destination registers being present.
- directly from instruction:
Fetch Cycle being present.
T0: MAR PC
T1: MDR [MAR] (memory read operation)
T2: IR MDR, PC PC + 4
This can could be done together given sufficient resources (data paths). Generally PC is a separate counter.
Implementing Execute Cycle being present.
Depends upon fetched instruction (in IR) Incorporating a signal to indicate particular instruction has been decoded, say INSTRi, in general we have:
INSTRi.T3: S T
INSTRi.T4: P Q
INSTRi.T5: R P
Execute cycle assumed to start at clock period T3.
General Arrangement for Execute Cycle being present.
Assumed to start at clock period T3:INSTRi.T3: S T
INSTRi.T4: P Q
INSTRi.T5: R P
More Specific being present.Example
Suppose op-codes are:
PC relative 101xxx
Register indirect 110xxx
where: aaa specifies arithmetic/logic operation
ccc specifies branch condition
xxx are don’t cares
Up to 7 operations allowed in this design
(00…00 = no-op)
In this particular case, can simply use a 3-8 line decoder: being present.
Questions being present.