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Chapter 3:. 22343 - Computer Organization & Design. Arithmetic For Computers. Signed Number Representations. –7 ≤ N ≤ +7. –(2 n –1 –1) ≤ N ≤ +( 2 n –1 –1). S Magnitude. 0 Magnitude. 1 2’s Complement. Sign-Magnitude Example : + 5 = – 5 = Range: 2’s Complement Example : + 5 =

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chapter 3

Chapter 3:

22343 - Computer Organization & Design

Arithmetic

For Computers

signed number representations
Signed Number Representations

–7 ≤ N ≤ +7

–(2n –1 –1) ≤ N ≤ +(2n –1 –1)

SMagnitude

0Magnitude

12’s Complement

  • Sign-Magnitude

Example:

+ 5 =

– 5 =

Range:

  • 2’s Complement

Example:

+ 5 =

– 5 =

signed number representations1
Signed Number Representations

8 Combinations

–(2n –1) ≤ N ≤ +(2n –1 –1)

8 Combinations

  • 2’s Complement

Range:

Exercise:

Calculate the range for 8 bits

2 s complement system
2’s Complement System
  • Used to represent integers, both positive & negative
  • Distinguish:

“2’s Comp. System” from “2’s Comp. Operation”

Example:

Represent the number +5 in 2’s Comp. System

Correct: Incorrect:

+5 = ( )2 +5 = ( )2

( )2

2 s complement system1
2’s Complement System

Example:

Given a number represented in 2’s comp. system, write an algorithm to square it.

Answer

addition
Addition

+ .

+ .

+ .

  • Bit-by-bit addition, with carry propagation.
  • Unsigned Binary Operands:
    • Produces unsigned binary
    • Possible overflow (Cy = 1)
  • Signed 2’s Comp. Operands:
    • Produces 2’s complement
    • Possible overflow

Cy Cy-1

subtraction
Subtraction

–.

 .

+ .

– .

 .

+ .

  • 2’s Complement Addition
  • Unsigned Binary Operands:
    • If Cy = 1, result is unsigned binary
    • If Cy = 0, result is negative (2’s comp)
    • No overflow
  • Signed 2’s Comp. Operands:
    • Produces 2’s complement
    • Possible overflow

Cy Cy-1

multiplication
Multiplication

×.

+ .

+ . .

+ ...

Partial Sum

0 1 1 0

× 0 1 0 1

0 1 1 0

0 0 0 0 .

0 1 1 0 . .

0 0 0 0 ...

+

0 0 0 0 0 0 0 0

=

  • Bit-by-bit Multiplication
  • Unsigned Binary Operands
    • Unsigned result
    • 2n-bit result from n × n bits operands
    • No overflow
    • Partial Sum
sequential multiplication
Sequential Multiplication

Multiplicand

Multiplier

1 1 1 1

× 0 1 0 1

1 1 1 1

0 0 0 0 .

0 1 1 0 . .

0 0 0 0 ...

0 0 0 0 1 1 1 1

0 1 0 1

ALU

Product

Control Unit

0 0 0 0 0 0 0 0

sequential multiplication1
Sequential Multiplication

Multiplicand

Multiplier

1 1 1 1

×0 1 0 1

1 1 1 1

0 0 0 0 .

1 1 1 1 . .

0 0 0 0 ...

0 0 0 0 1 1 1 1

0 1 0 1

1

Add

ALU

Product

Control Unit

Load

0 0 0 0 0 0 0 0

sequential multiplication2
Sequential Multiplication

Multiplicand

Multiplier

1 1 1 1

×0 1 0 1

1 1 1 1

0 0 0 0 .

1 1 1 1 . .

0 0 0 0 ...

Shift Left

Shift Right

0 0 0 0 1 1 1 1

0 1 0 1

ALU

Product

Control Unit

0 0 0 0 1 1 1 1

sequential multiplication3
Sequential Multiplication

Multiplicand

Multiplier

1 1 1 1

×0 1 0 1

1 1 1 1

0 0 0 0 .

1 1 1 1 . .

0 0 0 0 ...

Shift Left

Shift Right

0 0 0 11 1 1 0

0 0 1 0

0

ALU

Product

Control Unit

0 0 0 0 1 1 1 1

sequential multiplication4
Sequential Multiplication

Multiplicand

Multiplier

1 1 1 1

×0 1 0 1

1 1 1 1

0 0 0 0 .

1 1 1 1 . .

0 0 0 0 ...

Shift Left

Shift Right

0 0 111 1 00

00 0 1

1

Add

ALU

Product

Control Unit

Load

0 0 0 0 1 1 1 1

sequential multiplication5
Sequential Multiplication

Multiplicand

Multiplier

1 1 1 1

× 0 1 0 1

1 1 1 1

0 0 0 0 .

1 1 1 1 . .

0 0 0 0 ...

Shift Left

Shift Right

0 1111 000

000 0

0

ALU

Product

Control Unit

0 1001 0 1 1

sequential multiplication6
Sequential Multiplication

Multiplicand

Multiplier

1 1 1 1

×0 1 0 1

1 1 1 1

0 0 0 0 .

1 1 1 1 . .

0 0 0 0 . ..

1 0 0 1 0 1 1

1111 0000

0000

ALU

Product

Control Unit

0 1001 0 1 1

Delay: Number of Clocks = . . . . Clocks

sequential multiplication7
Sequential Multiplication

Multiplicand

Multiplier

0000 M M M M

m m m m

ALU

Product

Control Unit

0 0 0 0 0 0 0 0

Clock

Delay: Number of Clocks = . . . . Clocks

sequential multiplication8
Sequential Multiplication

Multiplicand

Multiplier

000 M M M M0

0 m m m

ALU

Product

Control Unit

0 0 0 0 p p p p

Clock

Delay: Number of Clocks = . . . . Clocks

sequential multiplication9
Sequential Multiplication

Multiplicand

Multiplier

00M M M M 00

00 m m

ALU

Product

Control Unit

0 0 p p p p p p

Clock

Delay: Number of Clocks = . . . . Clocks

sequential multiplication10
Sequential Multiplication

Multiplicand

Multiplier

0M M M M 000

000 m

ALU

Product

Control Unit

0 pp p p p p p

Clock

Delay: Number of Clocks = . . . . Clocks

sequential multiplication11
Sequential Multiplication

Multiplicand

Multiplier

M M M M 0000

0000

ALU

Product

Control Unit

ppp p p p p p

Clock

Delay: Number of Clocks = . . . . Clocks

multiplication1
Multiplication

0 1 1 0

× 0 1 0 1

Partial Sum: 0 0 0 0

0 0 0 0

+ 0 1 1 0

Partial Sum: 0 0 1 1 0

0 0 1 1 0

+ 0 0 0 0

Partial Sum: 0 0 1 1 0

0 0 1 1 0

+ 0 1 1 0

Partial Sum: 0 0 1 1 1 1 0

ALU Size?

signed multiplication
Signed Multiplication
  • Signed 2’s Comp. Operands:
    • Convert negative operands to positive values
    • Perform unsigned multiplication
    • Negate the result if the two operands differ in sign
division
Division

..

.│ 0

0

0

0

0

0

0

0

0

  • Subtract Divisor & Drop a Bit
  • Unsigned Binary Operands
    • Unsigned result
    • 2n-bit Dividend by n-bit divisor

 n-bit quotient and n-bit remainder

    • Possible overflow (big quotient)
      • Divide by zero
      • Quotient ≥ 2n
sequential division
Sequential Division

.0 1 1 0 1

0 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

1 0 1 0 0

– 0 1 1 0 0

0 1 0 0 0 0

– 0 1 1 0 0

0 0 1 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

0 1 0 1 0

– 0 1 1 0

0 1 0 0

Divisor

Quotient

0 1 1 0 0 0 0 0

0 0 0 0

ALU

Control Unit

0 1 0 1 0 0 1 0

Remainder

(Dividend)

sequential division1
Sequential Division

.0 1 1 0 1

0 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

1 0 1 0 0

– 0 1 1 0 0

0 1 0 0 0 0

– 0 1 1 0 0

0 0 1 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

0 1 0 1 0

– 0 1 1 0

0 1 0 0

Divisor

Quotient

0 1 1 0 0 0 0 0

0 0 0 0

Subtract

ALU

Load

Control Unit

0 1 0 1 0 0 1 0

Remainder

(Dividend)

sequential division2
Sequential Division

. 0 1 1 0 1

0 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

1 0 1 0 0

– 0 1 1 0 0

0 1 0 0 0 0

– 0 1 1 0 0

0 0 1 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

0 1 0 1 0

– 0 1 1 0

0 1 0 0

Divisor

Shift Right

Quotient

0 1 1 0 0 0 0 0

0 0 0 0

0

Shift Left

Add

ALU

Load

Control Unit

1 1 1 1 0 0 1 0

Remainder

sequential division3
Sequential Division

. 0 1 1 0 1

0 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

1 0 1 0 0

– 0 1 1 0 0

0 1 0 0 0 0

– 0 1 1 0 0

0 0 1 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

0 1 0 1 0

– 0 1 1 0

0 1 0 0

Divisor

Quotient

0 0 1 1 0 0 0 0

0 0 0 0

Subtract

ALU

Load

Control Unit

0 1 0 1 0 0 1 0

Remainder

sequential division4
Sequential Division

. 0 1 1 0 1

0 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

1 0 1 0 0

– 0 1 1 0 0

0 1 0 0 0 0

– 0 1 1 0 0

0 0 1 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

0 1 0 1 0

– 0 1 1 0

0 1 0 0

Divisor

Shift Right

Quotient

0 0 1 1 0 0 0 0

0 0 0 0

1

Shift Left

ALU

Control Unit

00 1 0 0 0 1 0

Remainder

sequential division5
Sequential Division

. 0 1 1 0 1

0 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

1 0 1 0 0

– 0 1 1 0 0

0 1 0 0 0 0

– 0 1 1 0 0

0 0 1 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

0 1 0 1 0

– 0 1 1 0

0 1 0 0

Divisor

Quotient

00 0 1 10 0 0

0 0 01

Subtract

ALU

Load

Control Unit

00 1 0 0 0 1 0

Remainder

sequential division6
Sequential Division

. 0 1 1 0 1

0 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

1 0 1 0 0

– 0 1 1 0 0

0 1 0 0 0 0

– 0 1 1 0 0

0 0 1 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

0 1 0 1 0

– 0 1 1 0

0 1 0 0

Divisor

Shift Right

Quotient

00 0 1 10 0 0

0 0 01

1

Shift Left

ALU

Control Unit

000 0 1 0 1 0

Remainder

sequential division7
Sequential Division

. 0 1 1 0 1

0 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

1 0 1 0 0

– 0 1 1 0 0

0 1 0 0 0 0

– 0 1 1 0 0

0 0 1 0 1 0

– 0 1 1 00

+ 0 1 1 0 0

0 1 0 1 0

– 0 1 1 0

0 1 0 0

Divisor

Quotient

000 0 110 0

0 011

Subtract

ALU

Load

Control Unit

000 0 1 0 1 0

Remainder

sequential division8
Sequential Division

. 0 1 1 0 1

0 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

1 0 1 0 0

– 0 1 1 0 0

0 1 0 0 0 0

– 0 1 1 0 0

0 0 1 0 1 0

– 0 1 1 00

+ 0 1 1 00

0 1 0 1 0

– 0 1 1 0

0 1 0 0

Divisor

Shift Right

Quotient

000 0 110 0

0 011

0

Shift Left

Add

ALU

Load

Control Unit

000 1 1 1 1 0

Remainder

sequential division9
Sequential Division

. 0 1 1 0 1

0 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

1 0 1 0 0

– 0 1 1 0 0

0 1 0 0 0 0

– 0 1 1 0 0

0 0 1 0 1 0

– 0 1 1 00

+ 0 1 1 00

1 0 1 0

– 0 1 1 0

0 1 0 0

Divisor

Quotient

0000 0110

0110

Subtract

ALU

Load

Control Unit

000 0 1 0 1 0

Remainder

sequential division10
Sequential Division

. 0 1 1 0 1

0 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

1 0 1 0 0

– 0 1 1 0 0

0 1 0 0 0 0

– 0 1 1 0 0

0 0 1 0 1 0

– 0 1 1 00

+ 0 1 1 00

1 0 1 0

– 0 1 1 0

0 1 0 0

Divisor

Shift Right

Quotient

0000 0110

0110

1

Shift Left

ALU

Control Unit

0000 0 1 00

Remainder

sequential division11
Sequential Division

. 0 1 1 01

0 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0

+ 0 1 1 0 0

1 0 1 0 0

– 0 1 1 0 0

0 1 0 0 0 0

– 0 1 1 0 0

0 0 1 0 1 0

– 0 1 1 00

+ 0 1 1 00

1 0 1 0

– 0 1 1 0

0 1 0 0

Divisor

Quotient

00000 011

1101

ALU

Control Unit

0000 0 1 00

Remainder

How many times was the Divisor & Quotient shifted?

How many clocks?

signed division
Signed Division
  • Signed 2’s Comp. Operands:
    • Convert negative operands to positive values
    • Perform unsigned division
    • Negate the result (?) if the two operands differ in sign
      • Which result? Quotient or remainder or both?
    • Dividend = Quotient × Divisor + Remainder
      • Example: 16 ÷ 3
    • Rule: Dividend & Remainder must have the same sign
floating point
Floating Point

.

× 10

.

× 2

  • Scientific Notation

Example: (10.5 × 10 – 7 is not good)

  • Normalized Scientific Notation

Example: (0.105 × 10 – 5 is not good)

  • Binary Numbers

Example: (0.0101 × 2 – 5 is not good)

(Normalized)

floating point1
Floating Point

±

?

S Exponent Fraction

32 bits

±

.

× 2

Sign & Magnitude

Overflow:The exponent is too large to be represented

Underflow:The exponent is too small to be represented

Single & Double Precision

ieee 754 floating point standard
IEEE 754 Floating Point Standard

32 bits

S Exponent Fraction

1

bit

8

bits

23

bits

255

0

= 0111 1111 (biased by 127)

+

0

256

Single Precision:

Biased Exponent

ieee 754 floating point standard1
IEEE 754 Floating Point Standard

This bit is always 1

No need to store it, hence implicit

S Exponent Fraction

0 1000 0101 0 0 1 0 1 1 0 • • • • 0

1 0111 1110 1 0 0 0 • • • • • • • 0

( )2

– ( )2

  • Implicit ‘1’

1.01 × 2 0

Examples:

75 =

– 0.75 =

0.0 = ?

ieee 754 floating point standard2
IEEE 754 Floating Point Standard

0 0000 0000 0 0 0 0 • • • • • • • 0

1111 1111 0 0 0 0 • • • • • • • 0

  • Reserved Bit Patterns
    • Zero:
    • ± Infinity:
    • Others like denormalized number and Not-a-Number
floating point addition subtraction
Floating-Point Addition / Subtraction

0 0111 1110 0 0 0 • • • 0

0 0111 1101 1 1 0 • • • 0

0 0111 1110 1.0 0 0 • • 0

0 0111 1101 1.1 1 0 • • 0

0 0111 1110 0.1 1 1 • • 0

0 0111 1110 1.1 1 1 • • 0

0 0111 1110 1 1 1 • • • 0

0.5 = ( )2 =

0.4375 = ( )2 =

× 2 –1

× 2 –1

0 0

× 2 –1

× 2 –1

  • Need to Align Decimal Points

Example:

Add 0.5 + 0.4375

Normalized Forms:

Align Decimal Point:

Perform Addition:

Normalize Result:

floating point multiplication
Floating-Point Multiplication

0 0111 1110 0 0 0 • • • 0

0 0111 1101 1 1 0 • • • 0

0 0111 11101.0 0 0 • • 0

0 0111 1101 1.1 1 0 • • 0

0 0111 1101 1.1 1 0 • • 0

0 0111 1100 1 1 0 • • • 0

0.5 = ( )2 =

0.4375 = ( )2 =

×.

+

– .

  • Need to Account for Biased Exponents

Example:

Multiply 0.5 × 0.4375

Normalized Forms:

Multiply Fractions:

Add Exponents:

Sub Extra Bias:

Round & Normalize:

chapter 31
Chapter 3

The End

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