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Changhwan Shin Department of Electrical Engineering and Computer Sciences University of California , Berkeley, CA 94720

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Dopant profiling and surface analysisof silicon nanowiresusing capacitance-voltage measurementsErik C. Garnett, Yu-Chih Tseng, Devesh R. Khanal, Junqiao Wu, Jeffrey Bokor, and Peidong Yang, Nature Nanotechnology, March 2009

Changhwan Shin

Department of Electrical Engineering and Computer Sciences

University of California, Berkeley, CA 94720

April 27, 2009

- Silicon nanowire structure and fabrication
- Structure
- Fabrication

- Dopant profiling and surface analysis
- C-V frequency-dependent measurement
- Principle behind dopant profiling
- Dopant profiling using high-frequency C-V measurement
- FEM 3-D C-V simulation

- Summary

Silicon nanowire structure and fabrication

Structure

Fabrication

Dopant profiling and surface analysis

C-V frequency-dependent measurement

Principle behind dopant profiling

Dopant profiling using high-frequency C-V measurement

FEM 3-D C-V simulation

Summary

3

- Device structure
- Gate dielectric
- Al2O3 (15nm), ALD

- Metal gate: Chromium
- Diameter ~75nm

- Gate dielectric

S

Lg~2.3µm

D

SOI

- Device Fabrication
- Growing SNW bridges epitaxially across patterend SOI trench,
- Using gold nanoparticles and vapour-liquid-solid (VLS) mechanism

- Hexagonal faceting of SNW ; <111> oriented wires
- But the surfaces appear to be {211}, instead of {110} in theory
- {211} commonly observed in micrometer-scale <111> oriented whiskers grown using the VLS mechnism.

- Growing SNW bridges epitaxially across patterend SOI trench,

Silicon nanowire structure and fabrication

Structure

Fabrication

Dopant profiling and surface analysis

C-V frequency-dependent measurement

Principle behind dopant profiling

Dopant profiling using high-frequency C-V measurement

FEM 3-D C-V simulation

Summary

5

- C-V measurement at 77K
- Freq. dispersion in the depletion region
- Substantial shift in C-V

- Increased Low-Freq. cap.
- Interface states (Not responding quickly to High-Freq. a.c.

- Freq. dispersion in the depletion region

- Interface state density, Dit, vs. E-Ev
- Using high-low method to extract Dit
- By comparing high/low-freq. cap. , Dit as a function of E is extracted.
- Due to underestimation of high-low method, lower bound of Dit is obtained.

- Decoupling interface state effects from strain/chemical gating/surface roughness

- Using high-low method to extract Dit

1e13 cm-2ev-1

Mid-gap

4e11 cm-2ev-1

Silicon nanowire structure and fabrication

Structure

Fabrication

Dopant profiling and surface analysis

C-V frequency-dependent measurement

Principle behind dopant profiling

Dopant profiling using high-frequency C-V measurement

FEM 3-D C-V simulation

Summary

7

- “Principle” behind profiling
- As SNW is depleted, the effective insulator thickness increases and the capacitance drops.
- Voltage dependence of the cap. drop is related to the majority carrier density: Rapid (slow) drop – low (high) dopant concentration.

8

Silicon nanowire structure and fabrication

Structure

Fabrication

Dopant profiling and surface analysis

C-V frequency-dependent measurement

Principle behind dopant profiling

Dopant profiling using high-frequency C-V measurement

FEM 3-D C-V simulation

Summary

9

- Radial dopant profile: Na diff/flat
- The expected dopant diffusion profile simulated using the experimental doping conditions as inputs (Na-diff.).
- Finite-element modeling (FEM) electrostatic simulations to calculate the corresponding majority carrier distribution (p(r) – diffusion).
- Carrier concentration extracted from the theoretical C-V curve with the simulated boron profile as an input (p(r) – simulated)

divergence

divergence

- Majority carrier profiling agreed well.
- Experimental data matches well to simulated data, but start to diverge towards the core.
- Divergence is expected according to the C-V dopant profile resolution limitation of twice the Debye screening length (Ld). Here, Ld is 2 and 13nm at the surface and core, respectively.

10

Silicon nanowire structure and fabrication

Structure

Fabrication

Dopant profiling and surface analysis

C-V frequency-dependent measurement

Principle behind dopant profiling

Dopant profiling using high-frequency C-V measurement

FEM 3-D C-V simulation

Summary

11

- FEM 3-D simulations
- Ideal C-V curve generated with diffusion/flat profiles
- In order to determine the flat band voltage (Vfb) and to validate the dopant profiling and Dit extraction.
- Extra capacitance came from direct coupling between the surround gate and the nanowire leads.
- Interface states causes minor deviation in slope.

20kHz

Extra capacitance

12

- C-V measurement to determine the Dit profile as a function of position in the band-gap.
- Comparable Dit of SNW to bulk MOSFET is critical for achieving high-performance electronic devices.
- Radial boron doping profile was measured via C-V curve and matched the expected profile from dopant diffusion simulation.

13

- Thank you for your attention!!!
- Questions?