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Accelerated Retention Test For SRAMs. Baosheng Wang PhD University of British Columbia, Vancouver, Canada ATI Technologies Inc. Agenda. SRAM Retention Fault Modeling Motivations Previous Work Review Proposed DFX Solutions Simplified Pause Test Retention-Aware Test Power Model

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Accelerated retention test for srams

Accelerated Retention TestFor SRAMs

Baosheng Wang

PhD

University of British Columbia, Vancouver, Canada

ATI Technologies Inc.


Agenda
Agenda

  • SRAM Retention Fault Modeling

  • Motivations

  • Previous Work Review

  • Proposed DFX Solutions

    • Simplified Pause Test

    • Retention-Aware Test Power Model

    • Pre-Discharge Write Test Mode (PDWTM)

      • Concepts

      • Implementations

      • Experimental Results

  • Conclusions


Retention faults modeling
Retention Faults Modeling

  • Failure to retain logic ZERO after some time

    • The delay time modeled as “TD0”

  • Failure to retain logic ONE after some time

    • The delay time modeled as “TD1”

  • Final delay modeled as TDF = max(TD0, TD1)

  • Generally, detected by performing a read operation after a certain TDF

    • The memory cell is idle during retention tests


Retention faults modeling cont
Retention Faults Modeling –cont.

What about writing ‘0’ followed by reading ‘0’?


Retention faults modeling cont1
Retention Faults Modeling –cont.

  • Opens at the PMOS conducting path

  • Fail to retain logic 0

  • Fail to retain logic 1

  • Opens at the power supply node


Agenda1
Agenda

  • SRAM Retention Fault Modeling

  • Motivations

  • Previous Work Review

  • Proposed DFX Solutions

    • Simplified Pause Test

    • Retention-Aware Test Power Model

    • Pre-Discharge Write Test Mode (PDWTM)

      • Concepts

      • Implementations

      • Experimental Results

  • Conclusions


Motivations
Motivations

  • SRAM Retention Testing

    • A must for highly reliable SRAMs

    • Time-consuming under the traditional pause test

  • Limited Benefits withCurrent Test Solutions

    • Long incremental test time

    • Incapability of at-speed retention testing

    • Other specific drawbacks

      • Inappropriate for embedded SRAMs

      • High design efforts, area overhead and performance penalties

      • Technology dependent


Agenda2
Agenda

  • SRAM Retention Fault Modeling

  • Motivations

  • Previous Work Review

  • Proposed DFX Solutions

    • Simplified Pause Test

    • Retention-Aware Test Power Model

    • Pre-Discharge Write Test Mode (PDWTM)

      • Concepts

      • Implementations

      • Experimental Results

  • Conclusions


Existing sram retention tests 1
Existing SRAM Retention Tests (1)

  • Algorithm-based solutions

    • w0/1 + pause time + r0/1 ([Zorian’95], etc.)

    • Use of read equivalent stress ([Dilillo’05])

  • DFT-based solutions

    • IDDx + specific algorithms ([Yoon’01], etc.)

    • Special write disturb scheme

      • Weak write test mode ([Meixner’96], etc.)

      • Low-speed PTEST mode ([Aitken’03], etc.)

    • Disabled read recovery + multiple reads ([Adams’04])


Existing sram retention tests 2
Existing SRAM Retention Tests (2)

  • Major drawbacks

    • Time-consuming

    • Can only be applied at slow speed

      • Bad detectability

      • Long test time

  • Other drawbacks

    • Algorithm-based solutions

      • Ineffective in small-size memory

      • Extra scheduling challenge

      • Loss in cell stability

    • DFT-based solutions

      • Non-compatible with traditional test algorithms

      • Large design effort, large test area overhead, etc.


Agenda3
Agenda

  • SRAM Retention Fault Modeling

  • Motivations

  • Previous Work Review

  • Proposed DFX Solutions

    • Simplified Pause Test

    • Retention-Aware Test Power Model

    • Pre-Discharge Write Test Mode (PDWTM)

      • Concepts

      • Implementations

      • Experimental Results

  • Conclusions


Simplified pause test 1
Simplified Pause Test (1)

Accessing Sequence

Disable

R0

W0

Traditional

Pause

Proposed

R0

W0

New Pause

Test Access

Pause = Test Access + New Pause


Simplified pause test 2
Simplified Pause Test (2)

  • A Case Study

    • SRAM: 128K words; 9/8 row/column addresses

    • Test: fast-row address sequencing test, 1ms pause time, 10ns test clock period

    • Test Access = 10ns *(29– 1)*28 = 1.308ms

    • Due to Test Access > 1ms, New Pause = 0 !!!

  • Disadvantage

    • Ineffective for a small-size SRAM


Agenda4
Agenda

  • SRAM Retention Fault Modeling

  • Motivations

  • Previous Work Review

  • Proposed DFX Solutions

    • Simplified Pause Test

    • Retention-Aware Test Power Model

    • Pre-Discharge Write Test Mode (PDWTM)

      • Concepts

      • Implementations

      • Experimental Results

  • Conclusions


Retention aware test power model 1
Retention-aware Test Power Model (1)

  • Previous test power model

    • Identical to that for other SoC core

    • Constant power consumption during test

    • Single-rectangle test power model

    • Overly pessimistic for e-SRAMs


Retention aware test power model 2
Retention-aware Test Power Model (2)

  • Unique for SRAMs (including e-SRAMs)

  • Incorporate retention fault test

  • “zero” power during the pause stages of retention test

  • Constant power during other stages

  • Three-rectangle test power model

  • T1 & T2: could be larger than the pause time


Retention aware test power model 3
Retention-aware Test Power Model (3)

  • Advantages

    • Simple and more accurate

    • Provide more freedom for optimal scheduling

    • More efficient for small-size e-SRAMs


Retention aware test power model 4
Retention-aware Test Power Model (4)

  • A Case Study

    • Using a pre-designed scheduling algorithm

    • Pause time = 100ms

    • Reduction factor = total time (“single-rectangle”) / total time (“three-rectangle”)

    • Replicate M1~M4 N times for multiple e-SRAMs case

(a) Using “single-rectangle” model

(b) Using “three-rectangle” model


Agenda5
Agenda

  • SRAM Retention Fault Modeling

  • Motivations

  • Previous Work Review

  • Proposed DFX Solutions

    • Simplified Pause Test

    • Retention-Aware Test Power Model

    • Pre-Discharge Write Test Mode (PDWTM)

      • Concepts

      • Implementations

      • Experimental Results

  • Conclusions


Pdwtm concepts 1

off

 off

PDWTM: Concepts (1)

Good Cell: Initial Status  W1

0

 Δ

1  0

off  on

 1

off  on

0(floating)

0 (solid)

0(floating)

1(pre-charge)

1(pre-charge)


Pdwtm concepts 2
PDWTM: Concepts (2)

Faulty Cell: Initial Status  W1

An Open

on

on

0

1

 0

0

 0

off  on

1  0

off  on

 off

 off

0(floating)

0 (solid)

0(floating)

0(floating)

0(solid)

1(pre-charge)

1(pre-charge)


Agenda6
Agenda

  • SRAM Retention Fault Modeling

  • Motivations

  • Previous Work Review

  • Proposed DFX Solutions

    • Simplified Pause Test

    • Retention-Aware Test Power Model

    • Pre-Discharge Write Test Mode (PDWTM)

      • Concepts

      • Implementations

      • Experimental Results

  • Conclusions


Pdwtm implementation i 1
PDWTM: Implementation I (1)

  • Pre-discharge during read cycle

    • Normal read cycle vs. read cycle under PDWTM

      • The first half cycle: read operation

      • The second half cycle: pre-charge vs. pre-discharge

March 9N + Pause

PDWMarch 9N

Improvement: reduced test time with maintained coverage


Pdwtm implementation i 2
PDWTM: Implementation I (2)

  • Pre-discharge during write cycle

    • Normal write cycle vs. write cycle under PDWTM

      • The first half cycle: write operation

      • The second half cycle: pre-charge vs. pre-discharge

March B

PDWMarch B

Improvement: increasedcoverage with maintained test time


Pdwtm implementation i 3
PDWTM: Implementation I (3)

  • Control Circuits

    • Maintain the original timing

    • Enter PDWTM with PDW_in = 1

      • Disable pre-charge circuits

      • Re-use write driver to pre-discharge bit lines

    • Extra FIVE logic gates and ONE external pin

    • Extra gate delay to pre-charge and write driver circuits


Pdwtm implementations ii 1
PDWTM: Implementations II (1)

  • No Write Recovery Test Mode (NWRTM)

    • Before a normal write cycle, add a No Write Recovery Cycle with a complementary value

    • E.g., W1, R1  NW0, W1, R1

March 9N + Pause

NWRMarch11N

Improvement: reduced test time with maintained coverage


Pdwtm implementations ii 2
PDWTM: Implementations II (2)

  • NWRTM: Control Circuits

    • Maintain the original timing

    • Enter NWRTM with PDWTM = 1

      • Disable pre-charge circuits

    • Extra ONE test cycle for each memory cell

    • Extra ONE external pin

    • Extra gate delay to pre-charge circuits


Agenda7
Agenda

  • SRAM Retention Fault Modeling

  • Motivations

  • Previous Work Review

  • Proposed DFX Solutions

    • Simplified Pause Test

    • Retention-Aware Test Power Model

    • Pre-Discharge Write Test Mode (PDWTM)

      • Concepts

      • Implementations

      • Experimental Results

  • Conclusions


Experiment al setup
Experimental Setup

  • DRF modelled as high impendence resistive opens

  • Spice Model

    • 1.8V 0.18um TSMC

    • 1.2V 0.13um UMC

  • Two extreme cells: high-speed and low-power

  • Assumptions

    • Expected bit line difference: 10% of power supply voltage

    • 50% test clock duty cycle

  • Selected comparison algorithms

    • March 9N + pause vs. PDWMarch 9N or NWRMarch 11N

    • March B vs. PDWMarch B


Experiment al sram model
Experimental SRAM Model

PRE_in

10/0.18

10/0.18

WL

BL

BLb

Memory Cell

1pF

1pF

WR0

WR1

10/0.18

10/0.18

Cell_LP (Width/Length: um)

Cell_HS (Width/Length: um)

Pull-up PMOS

0.22/0.18

0.22/0.18

Pull-down NMOS

0.22/0.18

0.405/0.18

Access NMOS

0.22/0.29

0.22/0.18


Experimental validations 1
Experimental Validations (1)

An open at pull-up PMOS

From a good cell

From a faulty cell

Detected!!!


Experimental validations 2
Experimental Validations (2)

An open at pull-up PMOS

From a good cell

From a faulty cell

Detected!!!


Experimental validations 3
Experimental Validations (3)

An open at power node

From a good cell

From a faulty cell

Detected!!!


Test t ime evaluations
Test Time Evaluations

  • Assumptions

    • A memory array: 128 word lines

    • 250ms delay time in the Pause Test

    • A 50ns test clock period

Test Patterns

Test Time

Pause Test

W0; Delay; R0; W1; Delay; R1

500ms

Weak Write Mode

W0; R0; W1; R1

26us

IDDQ Test

W0; R0; W1; R1

26us

NWRTM

NWR0; NWR1

<13us

PDWTM

Replacement the pre-charge phase

with the pre-discharge phase

PDWTM

0 us


Detectability evaluations
Detectability Evaluations

Detection Capability: Cell_LP (low-speed, at-speed)

/Cell_HS (low-speed, at-speed)

Opens

Test Algorithm

1000/100 Gohms

Pause

#1

PDWTM

(100, 10) / (100, 100) Kohms

1000/100 Gohms

Pause

#2

PDWTM

(100, 10) / (100, 100) Kohms

Undetectable

Pause

#3

PDWTM

(10, 1)/ (10, 10) Mohms


Other c ompariso ns
Other Comparisons

  • Design Effort

    • PDWTM: Global logic ONLY

    • WWR: Global logic + memory cell + WWR circuit

    • IDDQ: Global logic + current Sense Amplifier

  • Area penalty

    • PDWTM: Global logic ONLY

    • WWR, IDDQ: Global logic + Special DFT in each column I/O

  • Performance Impact

    • PDWTM: can be none

    • WWR, IDDQ: extra loading in I/O


Agenda8
Agenda

  • SRAM Retention Fault Modeling

  • Motivations

  • Previous Work Review

  • Proposed DFX Solutions

    • Simplified Pause Test

    • Retention-Aware Test Power Model

    • Pre-Discharge Write Test Mode (PDWTM)

      • Concepts

      • Implementations

      • Experimental Results

  • Conclusions


Conclusions 1
Conclusions (1)

  • Time-consuming SRAM retention testing

    • Current ineffective algorithm-based solutions

    • Current median-performance DFT techniques

      • Size-dependent incremental time

      • Incapable of running at-speed

      • Non-compatible with traditional test algorithms

  • Proposed DFX solutions features

    • Simplified pause test

      • Eliminate the pause time for retention testing in a large SRAM

    • Retention-aware test power model

      • Optimal scheduling with this model can yield full retention fault coverage with ZERO overhead


Conclusions 2
Conclusions (2)

  • Proposed DFX solutions features (PDWTM)

    • Zero-incremental time

      • Running at-speed

      • NO extra test cycles

    • Compared with the best know DFT techniques

      • Least design effort

      • Least area overhead

    • Easily merged into existing March algorithms

    • No negative impacts on general fault coverage



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