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FVTX Answers April 6th

FVTX Answers April 6th. What are the requirements for FVTX, from a performance/physics perspective ? What are the electronic requirements and can existing chip(s) be used for FVTX ?. Detector Requirements I. How many layers are needed ?

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FVTX Answers April 6th

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  1. FVTX Answers April 6th • What are the requirements for FVTX, from a performance/physics perspective ? • What are the electronic requirements and can existing chip(s) be used for FVTX ?

  2. Detector Requirements I • How many layers are needed ? • After the first round of simulations we came to the conclusion that we need 4 layers • Need at least 3 points for tracking • Need good efficiency (3 out of 4 points) • This is the current situation

  3. Detector Requirements II • What is the expected occupancy ? • What is the minimum segmentation required ? • The requirement is that the max occupancy be below 1 percent • The combined answer is that D.Lee did simulations which show that for the inner most ring in central Au+Au one reaches that goal for • 2 mm by 50 micron strips • Simulation had 0.5 mm Be and 2 barrel layers of 2% • Currently redoing that for more complete barrel in pisa

  4. Detector Requirements III • What is the required position resolution and what does this imply for the segmentation and the multiple-scattering (e.g. radiation thickness) of the first layer ? • The position resolution is driven by the decay physics • Separation between neutral and charge D-mesons (single muon) • Separation of J/psi from B-meson decay (secondary vertex) • Currently the 50 micron position resolution is the maximum useful resolution given the 300 micron thickness and the material in front • Redoing simulation to see the gain for thinner silicon m ct GeV mm D0 1865 125 D± 1869 317 B0 5279 464 B± 5279 496

  5. Electronics Requirements I • What is the required S/N ? • About 25/1 for a 150 micron detector • We are aiming for a maximum of 500 electrons • Keep occupancy due to noise as low as possible • What is the thermal requirement ? • Original HYTEC study for endcaps was performed for • 1/10 Watt/cm^2 for all silicon area • Current specification to keep cooling really simple • 1/10 Watt/cm^2 for the readout chip area !!!

  6. Electronics Requirements II • Multi-event buffering ?? • Current Phenix specification • 5 events with 4 buckets dead time inbeteen, i.e. all 500 ns • Asynchronous Readout speed 600 nsec for central Au+Au • 1 percent Occupancy in central Au+Au (10Khz for RHIC II) • 50 micro second hit spacing per chip …. • Asynchronous Readout speed for pp is 100 nsec • Large safety margin (full simulation to be started with FNAL)

  7. Electronics Requirements III • What about form factor? The maximum occupancy of 1 percent in central Au+Au dictates the 2 mm by 50 micron strip length • This strip length suggests a chip width of no more that 4 mm • Or is this really a criterion, since different geometries might be feasible if we forgo the bump-bonding ? • Yes and No  • We need to solve the bus challenge • We have 2 million channels (wires ????) • Maybe a mix between • Bumps for strips • Wires for bus • Overall conclusion, there is no existing chip that works for the endcap, need R&D together with FNAL

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